System and method for controlling common mode voltage via replica circuit and feedback control

Patent metadata

Field	Value
Publication number	US-9647618-B1
Application number	US-201615084910-A
Country	US
Kind code	B1
Filing date	Mar 30, 2016
Priority date	Mar 30, 2016
Publication date	May 9, 2017
Grant date	May 9, 2017

Abstract

The disclosure relates to a system and method for controlling a common mode voltage of an output differential signal of a differential signal processing circuit using a replica circuit and feedback control. The differential signal processing circuit includes two load devices, two input transistors, and two current-source transistors coupled in series between voltage rails, respectively. The replica circuit includes replica load device, replica input transistor, and replica current-source transistor coupled in series between the voltage rails. The common mode voltage of the input differential signal is applied to the replica input transistor to generate a replica output common mode voltage. A feedback circuit generates a bias voltage for the replica current-source transistor and the current-source transistors of the differential circuit to set and control the replica output common mode voltage and the output common mode voltage of the differential signal processing circuit to a target common mode voltage.

First claim

What is claimed is:

1. An apparatus, comprising:
a first differential signal processing circuit configured to generate a first output differential signal based on an input differential signal, comprising:
first and second load devices;
first and second input transistors including first and second control terminals configured to receive first and second components of the input differential signal, respectively; and
first and second current-source transistors coupled in series with the first and second load devices and the first and second input transistors between a first voltage rail and a second voltage rail, respectively;
wherein first and second components of the first output differential signal are configured to be generated at first and second nodes between the first and second load devices and the first and second input transistors, respectively; and

a first control circuit configured to control a first output common mode voltage of the first output differential signal by generating a first bias voltage for control terminals of the first and second current-source transistors from an input common mode voltage of the input differential signal.

2. The apparatus of claim 1 , wherein the first control circuit comprises:
a first replica load device;
a first replica input transistor including a first replica control terminal configured to receive the input common mode voltage of the input differential signal, wherein a first replica output common mode voltage is configured to be generated at a first replica node between the first replica load device and the first replica input transistor; and
a first replica current-source transistor coupled in series with the first replica load device and the first replica input transistor between the first voltage rail and the second voltage rail, wherein the first bias voltage is based on the first replica output common mode voltage, and wherein the first bias voltage is configured to be applied to a control terminal of the first replica current-source transistor.

3. The apparatus of claim 2 , wherein the first control circuit further comprises a first differential amplifier configured to generate the first bias voltage based on the first replica output common mode voltage and a first target output common mode voltage applied to respective inputs of the first differential amplifier.

4. The apparatus of claim 3 , wherein the first control circuit further comprises a voltage divider coupled between the first voltage rail and the second voltage rail, wherein the voltage divider is configured to generate the first target output common mode voltage.

5. The apparatus of claim 3 , wherein the first control circuit further comprises a voltage divider coupled between a third voltage rail and the second voltage rail, wherein the third voltage rail is configured to receive a bandgap reference voltage, and wherein the voltage divider is configured to generate the first target output common mode voltage.

6. The apparatus of claim 3 , further comprising:
a second differential signal processing circuit configured to generate a second output differential signal based on the first output differential signal, comprising:
third and fourth load devices;
third and fourth input transistors including third and fourth control terminals configured to receive the first and second components of the first output differential signal, respectively; and
third and fourth current-source transistors coupled in series with the third and fourth load devices and the third and fourth input transistors between the first voltage rail and the second voltage rail, respectively;
wherein first and second components of the second output differential signal are configured to be generated at third and fourth nodes between the third and fourth load devices and the third and fourth input transistors, respectively;

a second control circuit configured to control a second output common mode voltage of the second output differential signal by generating a second bias voltage for control terminals of the third and fourth current-source transistors from the first replica output common mode voltage or the first target output common mode voltage.

7. The apparatus of claim 6 , wherein the second control circuit comprises:
a second replica load device;
a second replica input transistor including a second replica control terminal configured to receive the first replica output common mode voltage or the first target output common mode voltage, wherein a second replica output common mode voltage is configured to be generated at a second replica node between the second replica load device and the second replica input transistor; and
a second replica current-source transistor coupled in series with the second replica load device and the second replica input transistor between the first voltage rail and the second voltage rail, wherein the second bias voltage is based on the second replica output common mode voltage, and wherein the second bias voltage is configured to be applied to a control terminal of the second replica current-source transistor.

8. The apparatus of claim 7 , wherein the second control circuit further comprises a second differential amplifier configured to generate the second bias voltage based on the second replica output common mode voltage and a second target output common mode voltage applied to respective inputs of the second differential amplifier.

9. The apparatus of claim 8 , wherein the second control circuit further comprises a voltage divider coupled between the first voltage rail and the second voltage rail, wherein the voltage divider is configured to generate the second target output common mode voltage.

10. The apparatus of claim 8 , wherein the second control circuit further comprises a voltage divider coupled between a third voltage rail and the second voltage rail, wherein the third voltage rail is configured to receive a bandgap reference voltage, and wherein the voltage divider is configured to generate the second target output common mode voltage.

11. The apparatus of claim 6 , wherein the second control circuit comprises:
a second replica load device;
a second replica input transistor including a second replica control terminal configured to receive the first replica output common mode voltage or the first target output common mode voltage, wherein a second replica output common mode voltage is configured to be generated at a third replica node between the second replica load device and the second replica input transistor; and
a second replica current-source transistor coupled in series with the second replica load device and the second replica input transistor between a third voltage rail and the second voltage rail, wherein the third voltage rail is configured to receive a bandgap reference voltage, wherein the second bias voltage is based on the second replica output common mode voltage, and wherein the second bias voltage is configured to be applied to a control terminal of the second replica current-source transistor.

12. The apparatus of claim 6 , wherein the second differential signal processing circuit comprises a continuous time linear equalizer (CTLE).

13. The apparatus of claim 12 , wherein the first differential signal processing circuit comprises a variable gain amplifier (VGA).

14. The apparatus of claim 1 , wherein the first differential processing circuit comprises a variable gain amplifier (VGA).

15. The apparatus of claim 1 , wherein the first control circuit comprises:
a first replica load device;
a first replica input transistor including a first replica control

Assignees

• Qualcomm Inc

Inventors

• Yuan Xiaobin
• Natonio Joseph
• Prasad Mangal
• Rasmus Todd Morgan

Classifications

• H03F3/45197 Primary

  Pl types (H03F3/45224, H03F3/45251 take precedence) · CPC title

• H03F2200/411

  the output amplifying stage of an amplifier comprising two power stages · CPC title

• H03F2200/453

  Controlling being realised by adding a replica circuit or by using one among multiple identical circuits as a replica circuit · CPC title

• H03F2203/45156

  At least one capacitor being added at the input of a dif amp · CPC title

• H03G1/0023

  in emitter-coupled or cascode amplifiers (H03G1/0029 takes precedence) · CPC title