Structure and method to reduce shorting and process degradation in STT-MRAM devices

Patent metadata

Field	Value
Publication number	US-10243138-B2
Application number	US-201815906154-A
Country	US
Kind code	B2
Filing date	Feb 27, 2018
Priority date	Nov 24, 2015
Publication date	Mar 26, 2019
Grant date	Mar 26, 2019

Abstract

A method of making a magnetic random access memory device includes forming a magnetic tunnel junction (MTJ) on an electrode, the MTJ including a reference layer, a tunnel barrier layer, and a free layer; disposing a hard mask on the MTJ; etching sidewalls of the hard mask and MTJ to form a stack with a first width and redeposit metal along the MTJ sidewall; depositing a sacrificial dielectric layer on the hard mask, surface of the electrode, exposed sidewall of the hard mask and the MTJ, and on redeposited metal along the sidewall of the MTJ; removing a portion of the sacrificial dielectric layer from sidewalls of the hard mask and MTJ and redeposited metal from the MTJ sidewalls; and removing a portion of a sidewall of the MTJ and hard mask to provide a second width to the stack; wherein the second width is less than the first width.

First claim

What is claimed is:

1. A method of making a magnetic random access memory (MRAM) device, the method comprising:
forming a magnetic tunnel junction (MTJ) on an electrode, the MTJ comprising a reference layer disposed in contact with the electrode, a tunnel barrier layer disposed on the reference layer, and a free layer disposed on the tunnel barrier layer;
disposing a hard mask on the MTJ;
etching sidewalls of the hard mask and the MTJ to form a stack with a first width and redeposit a metal along a sidewall of the MTJ;
depositing a sacrificial dielectric layer on a surface of the hard mask, a surface of the electrode, an exposed sidewall of the hard mask and MTJ, and on redeposited metal positioned along the sidewall of the MTJ;
performing a directional etch to remove a portion of the sacrificial dielectric layer from sidewalls of the hard mask and MTJ and the redeposited metal from sidewalls of the MTJ; and
depositing an encapsulating dielectric layer on the sacrificial dielectric layer, the encapsulating layer comprising a dielectric material that is different than the sacrificial dielectric layer.

2. The method of claim 1 , wherein the encapsulating dielectric layer is disposed on the sacrificial dielectric layer and exposed sidewalls of the hard mask and MTJ.

3. The method of claim 1 , wherein the sacrificial dielectric material is disposed directly in contact with a sidewall of the MTJ.

4. The method of claim 3 , wherein the encapsulating dielectric layer is disposed on the sacrificial dielectric material.

5. The method of claim 1 , wherein the sidewall of the tunnel barrier layer is substantially free of the redeposited metal.

6. The method of claim 1 , wherein the directional etch comprises an ion beam etch (IBE).

7. The method of claim 1 , wherein the sacrificial dielectric layer is silicon dioxide, silicon nitride, silicon oxynitride, aluminum oxide, or any combination thereof.

8. The method of claim 1 , wherein depositing the sacrificial dielectric layer comprises using a physical vapor deposition (PVD) method.

9. The method of claim 8 , wherein the PVD method comprises a temperature in a range from about 25 to about 300° C.

10. The method of claim 1 , wherein depositing the sacrificial dielectric layer comprises using a plasma enhanced chemical vapor deposition (PECVD) method.

Assignees

• IBM

Inventors

• Annunziata Anthony J
• Lauer Gen P
• Nowak Janusz J
• O'Sullivan Eugene J

Classifications

• H01L43/02

  Electricity · mapped topic

• H01L43/08 Primary

  Electricity · mapped topic

• H01L43/12

  Electricity · mapped topic

• H10N50/10 Primary

  Magnetoresistive devices · CPC title

• H10N50/01

  Manufacture or treatment · CPC title