Method for fabricating a flash memory

Patent metadata

Field	Value
Publication number	US-10243084-B2
Application number	US-201615279410-A
Country	US
Kind code	B2
Filing date	Sep 28, 2016
Priority date	Aug 13, 2014
Publication date	Mar 26, 2019
Grant date	Mar 26, 2019

Abstract

A method for fabricating semiconductor device is disclosed. First, a substrate is provided, and a dielectric stack is formed on the substrate, in which the dielectric stack includes a first silicon oxide layer and a first silicon nitride layer. Next, the dielectric stack is patterned, part of the first silicon nitride layer is removed to form two recesses under two ends of the first silicon nitride layer, second silicon oxide layers are formed in the two recesses, a spacer is formed on the second silicon oxide layers, and third silicon oxide layers are formed adjacent to the second silicon oxide layers.

First claim

What is claimed is:

1. A method for fabricating semiconductor device, comprising:
providing a substrate;
forming a dielectric stack on the substrate, wherein the dielectric stack comprises a first silicon oxide layer and a first silicon nitride layer directly contacting the first silicon oxide layer;
patterning the dielectric stack;
removing part of the first silicon oxide layer while simultaneously forming two recesses under two ends of the first silicon nitride layer, wherein the two recesses expose a top surface of the substrate;
forming second silicon oxide layers in the two recesses, wherein a bottom surface of the second silicon oxide layers is even with a bottom surface of the first silicon oxide layer;
forming a spacer on the second silicon oxide layers;
forming third silicon oxide layers adjacent to the second silicon oxide layers;
removing the first silicon nitride layer and the spacer after forming the third silicon oxide layers;
removing the second silicon oxide layers; and
forming a first tunnel oxide layer and a second tunnel oxide layer between the third silicon oxide layers and the first silicon oxide layer.

2. The method of claim 1 , further comprising:
forming a patterned resist on the dielectric stack;
using the patterned resist as mask to pattern the dielectric stack by removing part of the first silicon nitride layer;
performing a dry etching process to remove the first silicon oxide layer not covered by the first silicon nitride layer;
performing a wet etching process to remove part of the silicon oxide layer under the first silicon nitride layer for forming the two recesses under two ends of the first silicon nitride layer; and
stripping the patterned resist.

3. The method of claim 1 , further comprising performing an n-type implantation process after forming the second silicon oxide layers for forming a buried n+ region in the substrate.

4. The method of claim 1 , further comprising:
forming a second silicon nitride layer on the substrate, the second silicon oxide layers, and the first silicon nitride layer; and
removing part of the second silicon nitride layer while simultaneously forming the spacer made of the remnants of the second silicon nitride layer on the second silicon oxide layers and in the two recesses.

5. The method of claim 4 , wherein the spacer comprises an L-shape and a reverse L-shape.

6. The method of claim 1 , wherein the thickness of the third silicon oxide layers is greater than the thickness of the second silicon oxide layers.

7. The method of claim 1 , wherein the thickness of the third silicon oxide layers is greater than the thicknesses of the first tunnel oxide layer and the second tunnel oxide layer.

8. The method of claim 1 , wherein the thickness of the first silicon oxide layer is greater than the thicknesses of the first tunnel oxide layer and the second tunnel oxide layer.

9. The method of claim 1 , further comprising:
forming a floating gate on the first tunnel oxide layer, the second tunnel oxide layer, the third silicon oxide layers, and the first silicon oxide layer, an oxide-nitride-oxide (ONO) stack on the floating gate, and a control gate on the ONO stack;
forming a select gate adjacent to the first tunnel oxide layer; and
forming a drain region adjacent to the select gate and a source region adjacent to the third silicon oxide layers.

Assignees

• United Microelectronics Corp

Inventors

• Chen Chih-Jung
• Chen Tzu-Ping

Classifications

• G11C16/10

  Programming or data input circuits · CPC title

• G11C16/0466

  comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] (G11C16/0483, G11C16/0491 take precedence) · CPC title

• G11C16/14

  Circuits for erasing electrically, e.g. erase voltage switching circuits · CPC title

• G11C16/0408

  comprising cells containing floating gate transistors (G11C16/0483, G11C16/0491 take precedence) · CPC title

• G11C16/0416

  comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM · CPC title