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Split gate NAND flash memory structure and array, method of programming, erasing and reading thereof, and method of manufacturing
US9449693B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9449693-B2 |
| Application number | US-201414318502-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jun 27, 2014 |
| Priority date | May 20, 2005 |
| Publication date | Sep 20, 2016 |
| Grant date | Sep 20, 2016 |
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Abstract
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A split gate NAND flash memory structure is formed on a semiconductor substrate of a first conductivity type. The NAND structure comprises a first region of a second conductivity type in the substrate with a second region of the second conductivity type in the substrate, spaced apart from the first region. A continuous first channel region is defined between the first region and the second region. A plurality of floating gates are spaced apart from one another with each positioned over a separate portion of the channel region. A plurality of control gates are provided with each associated with and adjacent to a floating gate. Each control gate has two portions: a first portion over a portion of the channel region and a second portion over the associated floating gate and capacitively coupled thereto.
First claim
Opening claim text (preview).
What is claimed is: 1. A method of erasing a plurality of flash memory cells in a flash memory structure formed in a semiconductor substrate of a first conductivity type wherein said structure has a first region of a second conductivity type in said substrate; a second region of the second conductivity type in said substrate, spaced apart from said first region, thereby defining a continuous first channel region therebetween; a plurality of floating gates, spaced apart from one ano…
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- G11C16/0483Primary
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
- G11C16/10Primary
Physics · mapped topic
Physics · mapped topic
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Frequently asked questions
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- What does patent US9449693B2 cover?
- A split gate NAND flash memory structure is formed on a semiconductor substrate of a first conductivity type. The NAND structure comprises a first region of a second conductivity type in the substrate with a second region of the second conductivity type in the substrate, spaced apart from the first region. A continuous first channel region is defined between the first region and the second regi…
- Who is the assignee on this patent?
- Silicon Storage Tech Inc
- What technology area does this patent fall under?
- Primary CPC classification G11C16/0483. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Sep 20 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).