Heterogeneous integration using wafer-to-wafer stacking with die size adjustment

Patent metadata

Field	Value
Publication number	US-10243016-B2
Application number	US-201815952888-A
Country	US
Kind code	B2
Filing date	Apr 13, 2018
Priority date	May 6, 2016
Publication date	Mar 26, 2019
Grant date	Mar 26, 2019

Abstract

A method is provided for three-dimensional wafer scale integration of heterogeneous wafers with unequal die sizes that include a first wafer and a second wafer. The method includes manufacturing the second wafer in accordance with a periodicity that matches the periodicity of the first wafer. The method further includes placing, by a laser-based patterning device, a pattern in spaces between dies of the second wafer. The method also includes stacking the first wafer onto the second wafer. The first wafer includes logic circuitry, and the second wafer includes a backside illuminated image sensor.

First claim

What is claimed is:

1. A method for three-dimensional wafer scale integration of heterogeneous wafers with unequal die sizes that include a first wafer and a second wafer, the method comprising:
manufacturing the second wafer in accordance with a periodicity that matches the periodicity of the first wafer;
placing, by a laser-based patterning device, a pattern in spaces between dies of the second wafer; and
stacking the first wafer onto the second wafer,
wherein the first wafer comprises logic circuitry, and the second wafer comprises a backside illuminated image sensor.

2. The method of claim 1 , wherein said stacking step comprises:
bonding the first wafer face down onto a temporary carrier;
flipping and bonding the second wafer to the first wafer to form a wafer-to-wafer bonding;
removing the temporary carrier; and
flipping, singulating, and packaging the wafer-to-wafer bonding.

3. The method of claim 2 , wherein the first wafer comprises a plurality of dies, and the second wafer comprises another plurality of dies, and wherein said bonding step bonds the pluralities of dies in parallel.

4. The method of claim 2 , wherein said bonding step bonds the first wafer face down onto the temporary carrier using a temporary adhesive, and said removing step comprises removing the temporary adhesive.

5. The method of claim 2 , wherein a back face of the first wafer is bonded to a front face of the second wafer.

6. The method of claim 1 , wherein said stacking step comprises:
bonding the first wafer to the second wafer in a face-to-face configuration to form a wafer-to-wafer bonding; and
flipping, singulating, and packaging the wafer-to-wafer bonding.

7. The method of claim 6 , wherein said stacking step further comprises, in between said bonding step and said flipping step, thinning the first wafer using the second wafer as a handle to produce a thin first wafer in the wafer-to-wafer bonding.

8. The method of claim 6 , wherein the first wafer comprises a plurality of dies, and the second wafer comprises another plurality of dies, and wherein said bonding step bonds the pluralities of dies in parallel.

9. The method of claim 1 , wherein said placing step is performed to meet a pattern density requirement imposed on the second wafer.

10. The method of claim 1 , further comprising forming a Through-Silicon via connecting a portion of the first wafer to a portion of the second wafer.

11. The method of claim 1 , wherein said stacking step uses a copper-to-copper bonding process to bond the first wafer to the second wafer.

12. The method of claim 1 , wherein said stacking step comprises selectively bonding the first wafer to the second wafer face-to-face or back-to-face.

13. The method of claim 1 , further comprising thinning the first wafer to form a thin first wafer used for said stacking step.

14. A non-transitory computer readable storage medium comprising a computer readable program for three-dimensional wafer scale integration of heterogeneous wafers with unequal die sizes that include a first wafer and a second wafer, wherein the computer readable program when executed on a computer causes the computer to perform a method comprising:
manufacturing the second wafer in accordance with a periodicity that matches the periodicity of the first wafer;
placing, by a laser-based patterning device, a pattern in spaces between dies of the second wafer; and
stacking the first wafer onto the second wafer,
wherein the first wafer comprises logic circuitry, and the second wafer comprises a backside illuminated image sensor.

15. The non-transitory computer readable storage medium of claim 14 , wherein said stacking step comprises:
bonding the first wafer face down onto a temporary carrier;
flipping and bonding the second wafer to the first wafer to form a wafer-to-wafer bonding;
removing the temporary carrier; and
flipping, singulating, and packaging the wafer-to-wafer bonding.

16. The non-transitory computer readable storage medium of claim 15 , wherein the first wafer comprises a plurality of dies, and the second wafer comprises another plurality of dies, and wherein said bonding step bonds the pluralities of dies in parallel.

17. The non-transitory computer readable storage medium of claim 14 , wherein said stacking step comprises:
bonding the first wafer to the second wafer in a face-to-face configuration to form a wafer-to-wafer bonding; and
flipping, singulating, and packaging the wafer-to-wafer bonding.

18. The non-transitory computer readable storage medium of claim 17 , wherein said stacking step further comprises, in between said bonding step and said flipping step, thinning the first wafer using the second wafer as a handle to produce a thin first wafer in the wafer-to-wafer bonding.

19. The non-transitory computer readable storage medium of claim 17 , wherein the first wafer comprises a plurality of dies, and the second wafer comprises another plurality of dies, and wherein said bonding step bonds the pluralities of dies in parallel.

20. The non-transitory computer readable storage medium of claim 14 , further comprising forming a Through-Silicon via connecting a portion of the first wafer to a portion of the second wafer.

Assignees

• IBM

Inventors

• Kumar Arvind
• Lamorey Mark

Classifications

• H01L27/14687

  Electricity · mapped topic

• H01L27/14698

  Electricity · mapped topic

• H01L27/1464

  Electricity · mapped topic

• H01L27/14634 Primary

  Electricity · mapped topic

• H01L27/1469

  Electricity · mapped topic