Structure featuring ferroelectric capacitance in interconnect level for steep sub-threshold complementary metal oxide semiconductor transistors

Patent metadata

Field	Value
Publication number	US-10242990-B2
Application number	US-201715815312-A
Country	US
Kind code	B2
Filing date	Nov 16, 2017
Priority date	Feb 3, 2017
Publication date	Mar 26, 2019
Grant date	Mar 26, 2019

Abstract

After forming a first functional gate stack located on a first body region of a first semiconductor material portion located in a first region of a substrate and a second functional gate stack located on a second body region of a second semiconductor material portion located in a second region of the substrate, a ferroelectric gate interconnect structure is formed connecting the first functional gate stack and the second functional gate stack. The ferroelectric gate interconnect structure includes a U-shaped bottom electrode structure, a U-shaped ferroelectric material liner and a top electrode structure.

First claim

What is claimed is:

1. A semiconductor structure comprising:
a functional gate stack located on a body region of a semiconductor material portion located on a substrate and surrounded by an interlevel dielectric (ILD) layer; and
a ferroelectric gate contact structure located in a contact level dielectric layer present on the ILD layer, wherein the ferroelectric gate contact structure directly contacts a portion of a topmost surface of the functional gate stack that is located outside of the first semiconductor portion,
wherein the ferroelectric gate contact structure comprises a bottom electrode structure, a ferroelectric material liner and a top electrode structure, and wherein the bottom electrode structure, the ferroelectric material liner and the top electrode structure have a topmost surface that is coplanar with each other.

2. The semiconductor structure of claim 1 , wherein outermost sidewalls of the functional gate stack are offset from outermost sidewalls of the ferroelectric gate contact structure.

3. The semiconductor structure of claim 1 , wherein the ferroelectric material liner comprises a ferroelectric material that generates a negative capacitance.

4. The semiconductor structure of claim 3 , wherein the ferroelectric material comprises a mixed metal oxide.

5. The semiconductor structure of claim 4 , wherein the mixed metal oxide comprises BaTiO 3 , Pb[Zr x Ti 1-x ]O 3 (0≤x≤1), SrBi 2 Ta 2 O 9 .

6. The semiconductor structure of claim 4 , wherein the mixed metal oxide comprises crystalline HfO 2 that contains a doping element selected from the group consisting of Zr, Al, Ca, Ce, Dy, Er, Gd, Ge, La, Sc, Si, Sr, Sn, and Y.

7. The semiconductor structure of claim 4 , wherein each of the bottom and top electrodes comprises a conductive material.

8. The semiconductor structure of claim 7 , wherein the conductive material comprises tungsten, aluminum, copper or alloys thereof.

9. The semiconductor structure of claim 1 , wherein the semiconductor material portion comprises a semiconductor fin.

10. The semiconductor structure of claim 1 , further comprising source/drain regions located laterally adjacent the body region and within the semiconductor material portion.

11. The semiconductor structure of claim 10 , further comprising raised/source/drain regions located on the source/drain regions.

12. A semiconductor structure comprising:
a first functional gate stack located on a body region of a first semiconductor material portion located on a substrate and surrounded by an interlevel dielectric (ILD) layer;
a second functional gate stack located on a body region of a second semiconductor material portion located on the substrate and surrounded by the interlevel dielectric (ILD) layer;
a third functional gate stack located on a body region of a third semiconductor material portion located on the substrate and surrounded by the interlevel dielectric (ILD) layer;
a fourth gate stack located on a body region of a fourth semiconductor material portion located on the substrate and surrounded by the interlevel dielectric (ILD) layer;
a ferroelectric gate contact structure directly contacting a portion of a topmost surface of the first functional gate stack that is located outside the first semiconductor portion and a portion of a topmost surface of the second functional gate stack that is located outside the second semiconductor material portion; and
a metal gate interconnect structure contacting the third and fourth gate stacks.

13. The semiconductor structure of claim 12 , wherein the ferroelectric gate contact structure comprises a bottom electrode structure, a ferroelectric material liner and a top electrode structure, and wherein the bottom electrode structure, the ferroelectric material liner and the top electrode structure have a topmost surface that is coplanar with each other.

14. The semiconductor structure of claim 13 , wherein the ferroelectric material liner comprises a ferroelectric material that generates a negative capacitance.

15. The semiconductor structure of claim 14 , wherein the ferroelectric material comprises a mixed metal oxide.

16. The semiconductor structure of claim 15 , wherein the mixed metal oxide comprises BaTiO 3 , Pb[Zr x Ti 1-x ]O 3 (0≤x≤1), SrBi 2 Ta 2 O 9 .

17. The semiconductor structure of claim 15 , wherein the mixed metal oxide comprises crystalline HfO 2 that contains a doping element selected from the group consisting of Zr, Al, Ca, Ce, Dy, Er, Gd, Ge, La, Sc, Si, Sr, Sn, and Y.

Assignees

• IBM

Inventors

• Ando Takashi
• Balakrishnan Karthik
• Hashemi Pouya
• Reznicek Alexander

Classifications

• H10D84/813

  Combinations of field-effect devices and capacitor only · CPC title

• H10D84/85

  Complementary IGFETs, e.g. CMOS · CPC title

• H10B51/30 Primary

  characterised by the memory core region · CPC title

• H01L29/0649

  Electricity · mapped topic

• H01L27/092

  Electricity · mapped topic