Interconnect structure and semiconductor structures for assembly of cryogenic electronic packages

Patent metadata

Field	Value
Publication number	US-10242968-B2
Application number	US-201715684393-A
Country	US
Kind code	B2
Filing date	Aug 23, 2017
Priority date	Nov 5, 2015
Publication date	Mar 26, 2019
Grant date	Mar 26, 2019

Abstract

A cryogenic electronic package includes at least two superconducting and/or conventional metal semiconductor structures. Each of the semiconductor structures includes a substrate and a superconducting trace. Additionally, each of the semiconductor structures includes a passivation layer and one or more under bump metal (UBM) structures. The cryogenic electronic package also includes one or more superconducting and/or conventional metal interconnect structures disposed between selected ones of the at least two superconducting semiconductor structures. The interconnect structures are electrically coupled to respective ones of the UBM structures of the semiconductor structures to form one or more electrical connections between the semiconductor structures. A method of fabricating a cryogenic electronic package is also provided.

First claim

What is claimed is:

1. A cryogenic electronic package, comprising:
at least two superconducting and/or conventional metal semiconductor structures, each of the semiconductor structures including:
a substrate having first and second opposing surfaces;
a superconducting trace having first and second opposing surfaces, wherein the first surface of the superconducting trace is disposed over the second surface of the substrate;
a passivation layer having first and second opposing surfaces and one or more openings formed in selected portions of the passivation layer, wherein the first surface of the passivation layer is disposed over the second surface of the superconducting trace, and the passivation layer openings extend from the second surface of the passivation layer to the second surface of the superconducting trace over which the first surface of the passivation layer is disposed; and
one or more under bump metal (UBM) structures disposed in respective ones of the passivation layer openings, wherein the UBM structures are electrically coupled to the second surface of the superconducting trace, and have a surface disposed over selected portions of the second surface of the passivation layer surrounding edges of the passivation layer openings; and

one or more superconducting and/or conventional metal interconnect structures disposed between selected ones of the at least two semiconductor structures, and electrically coupled to respective ones of the UBM structures of the semiconductor structures to form one or more electrical connections between the semiconductor structures, wherein a first respective one of the electrical connections formed between a first one of the semiconductor structures and a second one of the semiconductor structures includes: the superconducting trace of the first one of the semiconductor structures, a first one of the UBM structures of the first one of the semiconductor structures, a second one of the UBM structures of the second one of the semiconductor structures, the superconducting trace of the second one of the semiconductor structures, and a first respective one of the interconnect structures coupled to the first and second ones of the UBM structures, and wherein a contact area between the interconnect structures and the respective ones of the UBM structures of the semiconductor structures to which the interconnect structures are coupled is provided as having one of:
a circular shape; and
a rectangular or square shape, wherein in the case of a circular-shape contact area, a diameter of the contact area is greater than a width of the semiconductor trace of the semiconductor structures, and in the case of a rectangular—or square-shaped contact area, a width of the contact area is greater than a width of the semiconductor trace of the semiconductor structures such that in response to a critical current flow at the superconducting trace of the first superconducting structure, a substantially same critical current flows from the first superconducting structure through the interconnect structures such that a substantially same critical current flows through both the superconducting trace of the first semiconductor structure and the superconducting trace of the second semiconductor structure;
wherein at least one of the one or more interconnect structure has a diameter that is less than a diameter of the UBM structure to which it is coupled.

2. The cryogenic electronic package of claim 1 wherein the UBM structures have openings shaped to receive the interconnect structures, and the UBM structures include:
a first pad portion having a surface disposed over the second surface of the superconducting trace;
one or more second pad portions having a surface disposed over the selected portions of the second surface of the passivation layer; and
one or more pad interconnects extending from the first pad portion to the second pad portions, wherein the UBM structure openings extend between the first and second pad portions of the UBM structures.

3. The cryogenic electronic package of claim 2 wherein the interconnect structures are received in the UBM structure openings.

4. The cryogenic electronic package of claim 3 wherein the UBM structure openings have a first associated diameter, and the interconnect structures have a second associated diameter that is substantially less than the first diameter.

5. The cryogenic electronic package of claim 2 wherein the semiconductor structures further comprise:
an interconnect pad disposed between the second surface of the substrate and the first surface of the superconducting trace such that the first respective one of the electrical connections formed between the first one of the semiconductor structures and the second one of the semiconductor structures further includes: the interconnect pad of the first one of the semiconductor structures, and the interconnect pad of the second one of the semiconductor structures such that the electrical connection include first superconducting trace-first superconducting pad-first UBM structure-interconnect structure-second UBM structure-second superconducting pad-second superconducting trace.

6. The cryogenic electronic package of claim 5 wherein the interconnect pad has first and second opposing surfaces, with the first surface of the interconnect pad disposed proximate to the second surface of the substrate, and the second surface of the interconnect pad disposed proximate to the first surface of the superconducting trace, and wherein the first pad portion of the UBM structures has first and second opposing surfaces, with the first surface corresponding to the surface of the first pad portion disposed over the second surface of the superconducting trace, wherein the first and second surfaces of the interconnect pad each have a first associated diameter, and the first and second surfaces of the first pad portion each have a second associated diameter that is substantially less than the first diameter.

7. The cryogenic electronic package of claim 1 wherein the interconnect structures are disposed over and coupled to first selected ones of the UBM structures of the selected ones of the semiconductor structures prior to coupling the first selected ones of the UBM structures to second selected ones of the UBM structures of the semiconductor structures to form the electrical connections, wherein at least one of the interconnect structures includes a superconducting, partially superconducting and/or conventional metal bump.

8. The cryogenic electronic package of claim 1 wherein the interconnect structures include a first interconnect portion and a second interconnect portion, wherein the first interconnect portion is disposed over and coupled to first selected ones of the UBM structures of the selected ones of the semiconductor structures, and the second interconnect portion is disposed over and coupled to second selected ones of the UBM structures of the selected ones of the semiconductor structures,
wherein the first interconnect portion has a first melting point, the second interconnect portion has a second melting point, and the interconnect structures including the first interconnect portion and the second interconnect portion has a third melting point and concentration gradient at the coupling surface of the second interconnect section that is different from both the first melting point and the second melting point when the first and second interconnect portions are coupled together during coupling of the semiconductor structures, wherein at least one of the first and second interconnect portions includes a superconducting bump.

9. The cryogenic electronic package of claim 1 wherein the interconnect structures are provided having a critic

Assignees

• Massachusetts Inst Technology

Inventors

• Das Rabindra N
• Dauler Eric A

Classifications

• H10W20/216

  characterised by dielectric material at least partially filling the via holes, e.g. covering the through-semiconductor vias in the via holes · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/22

  the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL · CPC title

• H10W90/28

  the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape · CPC title

• H10W90/293

  characterised by non-galvanic coupling between the chips, e.g. capacitive coupling · CPC title