LDMOS transistor and method

Patent metadata

Field	Value
Publication number	US-10242932-B2
Application number	US-201615191989-A
Country	US
Kind code	B2
Filing date	Jun 24, 2016
Priority date	Jun 24, 2016
Publication date	Mar 26, 2019
Grant date	Mar 26, 2019

Abstract

In an embodiment, a semiconductor device includes a semiconductor substrate having a front surface, a LDMOS transistor arranged in the front surface of the substrate and having an intrinsic source, and a through substrate via. A first conductive layer lines sidewalls of the through substrate via and extends from the through substrate via onto the front surface of the semiconductor substrate and is electrically coupled with the intrinsic source.

First claim

What is claimed is:

1. A method for electrically coupling an electrode of a transistor structure arranged at a first surface of a substrate to a third conductive layer arranged at a second surface of the substrate opposing the first surface, the method comprising:
forming a blind via in the substrate adjacent the transistor structure;
depositing a first conductive layer onto side walls of the blind via and a region of a second conductive layer arranged on the first surface of the substrate adjacent the blind via and coupled to the electrode of the transistor structure, the first conductive layer consists of a single integral unit consisting of a same material throughout;
working the second surface of the substrate so as to expose a portion of the first conductive layer; and
depositing the third conductive layer onto the second surface of the substrate and the portion of the first conductive layer so as to electrically couple the third conductive layer with the electrode of the transistor structure,
wherein the transistor structure is a LDMOS (Lateral Diffused Metal Oxide Semiconductor) transistor structure and the electrode is a highly doped source region of a silicon substrate, wherein the source region has a doping concentration of at least 5·10 19 cm −3 ,
wherein the single integral unit of the first conductive layer directly contacts a sidewall of the blind via and directly contacts a portion of the first surface of the substrate between the sidewall of the blind via and the region of the second conductive layer arranged on the first surface.

2. The method of claim 1 , wherein the first conductive layer has a thickness t1 and the second conductive layer has a thickness t2, wherein t1≥5t2.

3. The method of claim 2 , wherein the first conductive layer comprises copper and the second conductive layer comprises Ti.

4. The method of claim 1 , wherein the first conductive layer is deposited by electroplating.

5. The method of claim 1 , further comprising:
applying a mask to the first surface such that an opening is positioned over the blind via and the region of the second conductive layer and such that the electrode of the transistor structure is covered by the mask;
applying the first conductive layer into the opening of the mask; and
planarising the first surface of the substrate such that an upper surface of the first conductive layer is substantially coplanar with an upper surface of an oxide layer arranged on the first surface of the substrate.

6. The method of claim 1 , further comprising:
depositing a multilayer liner into the blind via and onto the region of the second conductive layer on the first surface of the substrate adjacent the via; and
depositing the first conductive layer onto the multilayer liner.

7. The method of claim 6 , wherein a portion of the multilayer liner deposited onto side walls of the blind via has a different number of layers than a portion of the multilayer liner deposited on the region of the second conductive layer on the first surface of the substrate.

8. The method of claim 1 , wherein the first conductive layer is coupled to a source electrode of the transistor structure.

9. The method of claim 1 , wherein the silicon substrate has a bulk resistivity p≥100 Ohm·cm.

10. The method of claim 1 , wherein the first conductive layer is fabricated using dual Damascene techniques such that it extends vertically through the substrate from the second surface to the first surface and laterally from the blind via on the first surface in a direction of the electrode of the transistor structure.

11. The method of claim 1 , wherein the first conductive layer provides a redistribution path that has a vertical portion within the blind via and a lateral portion on the first surface of the substrate.

12. The method of claim 11 , wherein the vertical portion and the lateral portion are formed using a single deposition process.

13. The method of claim 1 , wherein the single integral unit of the first conductive layer covers and directly contacts the region of the second conductive layer arranged on the first surface.

Assignees

• Infineon Technologies Ag

Inventors

• Birner Albert
• Brech Helmut
• Zigldrum Matthias

Classifications

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• H10W20/4421

  the principal metal being copper · CPC title

• H10W20/023

  the interconnections being through-semiconductor vias · CPC title

• H10W20/0245

  comprising use of blind vias during the manufacture · CPC title

• H10W20/0261

  characterised by the filling method or the material of the conductive fill · CPC title