Adaptive power down of intra-chip interconnect

Patent metadata

Field	Value
Publication number	US-10241561-B2
Application number	US-201715620950-A
Country	US
Kind code	B2
Filing date	Jun 13, 2017
Priority date	Jun 13, 2017
Publication date	Mar 26, 2019
Grant date	Mar 26, 2019

Abstract

The hash function used by the processors on a multi-processor chip to distribute accesses to the various last-level caches via the links is changed according to which last-level caches (and/or links) that are active (e.g., ‘on’) and which are in a lower power consumption mode (e.g., ‘off’.) A first hash function is used to distribute accesses to all of the last-level caches and all of the links when all of the last-level caches are ‘on.’ A second hash function is used to distribute accesses to the appropriate subset of the last-level caches and corresponding subset of links when some of the last-level caches are ‘off.’ Data can be sent to only the active last-level caches via active links. By shutting off links connected to caches and components that are in a lower power consumption mode, the power consumption of the chip is reduced.

First claim

What is claimed is:

1. An integrated circuit, comprising:
a plurality of last-level caches that can be placed in at least a first high cache-power consumption mode and a first low cache-power consumption mode, the plurality of last-level caches including a first last-level cache and a second last-level cache;
a plurality of processor cores to access data in the plurality of last-level caches; and,
an interconnect network, comprised of a plurality of point-to-point links that can be placed in at least a first high link-power consumption mode and a first low link-power consumption mode, to receive access addresses from the plurality of processor cores and to couple, via respective subsets of the plurality of point-to-point links, each of the plurality of processor cores to a respective one of the plurality of last-level caches, a first subset of the plurality of point-to-point links to be placed in the first low link-power consumption mode based at least in part on the first last-level cache being in the first low cache-power consumption mode.

2. The integrated circuit of claim 1 , wherein the plurality of processor cores are to access data in the plurality of last-level caches according to a first hashing function that maps processor access addresses to respective ones of the plurality of last-level caches based at least in part on all of the last-level caches being in the first high power consumption mode, the plurality of processor cores to access data in the plurality of last-level caches according to a second hashing function that maps processor access addresses to a subset of the plurality of last-level caches based at least in part on the first last-level cache being in the first low cache-power consumption mode.

3. The integrated circuit of claim 1 , wherein a first processor core of the plurality of processor cores is more tightly coupled to the first last-level cache than to a first set of last-level caches of the plurality of last-level caches.

4. The integrated circuit of claim 3 , wherein the first subset of the plurality of point-to-point links comprise at least one point-to-point link used to couple the first last-level cache to at least one of the first set of last-level caches.

5. The integrated circuit of claim 4 , wherein the plurality of point-to-point links are configured as a fully connected mesh and the first subset includes ones of the plurality of point-to-point links that directly couple the first last-level cache to the first set of last-level caches.

6. The integrated circuit of claim 3 , wherein the first set last-level caches that are not more tightly coupled to the first processor core than the first last-level cache includes the second last-level cache, a second processor core of the plurality of processor cores being more tightly coupled to the second last-level cache than to a second set of last-level caches of the plurality of last-level caches.

7. The integrated circuit of claim 6 , wherein the first subset of the plurality of point-to-point links includes point-to-point links used to couple the first last-level cache to the first subset and does not include point-to-point links used to couple the second last-level cache to the second subset.

8. A method of operating a processing system having a plurality of processor cores, comprising:
based at least in part on a first set of last-level caches of a plurality of last-level caches being in a first power consumption mode, using a first set of links to route accesses by a first processor core of the plurality of processor cores to the first set of last-level caches; and,
based at least in part on a second set of last-level caches of the plurality of last-level caches being in the first power consumption mode, using a second set of links to route accesses by the first processor core to the second set of last-level caches.

9. The method of claim 8 , wherein the first processor core is more tightly coupled to a first one of the plurality of last-level caches than to other last-level caches of the plurality of last-level caches.

10. The method of claim 9 , wherein the first one of the plurality of last-level caches is in both the first set of last-level caches and the second set of last-level caches.

11. The method of claim 8 , wherein the first processor core is more tightly coupled to a first one of the plurality of last-level caches than to other last-level caches of the plurality of last-level caches and a second processor core is more tightly coupled to a second one of the plurality of last-level caches than to other last-level caches of the plurality of last-level caches.

12. The method of claim 11 , wherein the second last-level cache is in the first set of last-level caches and is not in the second set of last-level caches.

13. The method of claim 12 , wherein a difference between the second set of links and the first set of links includes at least one link used to route accesses between the first processor core and the second last-level cache.

14. The method of claim 13 , wherein the first set of links are configured to form a fully connected mesh network between the first processor core of the plurality of processor cores and the first set of last-level caches, and the second set of links are configured to form a fully connected mesh network between the first processor core of the plurality of processor cores and the second set of last-level caches.

15. The method of claim 14 , wherein the second set of links are configured such that the second set of links does not route accesses by the first processor core to the second last-level cache.

16. A method of operating a plurality of processor cores on an integrated circuit, comprising:
distributing accesses by a first processor core to a first set of last-level caches of a plurality of last-level caches using a first set of links that are in a first power consumption mode, the first processor core associated with a first last-level cache of the plurality of last-level caches;
distributing accesses by a second processor core to the first set of last-level caches using the first set of links that are in the first power consumption mode, the second processor core associated with a second last-level cache of the plurality of last-level caches;
placing the second last-level cache in a second power consumption mode; and,
while the second last-level cache is in the second power consumption mode, distributing accesses by the first processor core to a second set of last-level caches using a second set of links that are in the first power consumption mode, the second set of links not providing a path to distribute accesses by the first processor core to the second last-level cache.

17. The method of claim 16 , wherein the first set of links that are in the first power consumption mode fully connect the first processor core to the first set of last-level caches and the first set of last-level caches includes the second last-level cache.

18. The method of claim 17 , wherein the second set of links that are in the first power consumption mode fully connect the first processor core to the second set of last-level caches and the second set of last-level caches does not include the second last-level cache.

19. The method of claim 16 , wherein while the second last-level cache is in the second power consumption mode, a third set of links are in a low power consumption mode.

20. The method of claim 19 , wherein the third set of links is to be included in the first set of links and is not to be included in the

Assignees

• Microsoft Technology Licensing Llc

Inventors

• Lai Patrick P
• Shearer Robert Allen

Classifications

• G06F1/3243 Primary

  Power saving in microcontroller unit · CPC title

• G06F12/0897

  with two or more cache hierarchy levels (with multilevel cache hierarchies G06F12/0811) · CPC title

• G06F1/3203

  Power management, i.e. event-based initiation of a power-saving mode · CPC title

• G11C5/148

  Details of power up or power down circuits, standby circuits or recovery circuits · CPC title

• G06F1/3293

  by switching to a less power-consuming processor, e.g. sub-CPU · CPC title