Virtual access of input/output (I/O) for test via an on-chip star network

Patent metadata

Field	Value
Publication number	US-10241148-B2
Application number	US-201514824044-A
Country	US
Kind code	B2
Filing date	Aug 11, 2015
Priority date	Aug 11, 2015
Publication date	Mar 26, 2019
Grant date	Mar 26, 2019

Abstract

One embodiment of the present invention sets forth an integrated circuit that includes multiple input/output (I/O) pad groups. Each I/O pad group includes an on-chip star network, multiple I/O pads, multiple test multiplexers, a digital-to-analog converter (DAC), and a wide-range comparator. Each test multiplexer is configured to couple a different I/O pad to the on-chip star network. The DAC is configured to supply at least one of a source current, a sink current, and a first reference voltage to the on-chip star network. The wide-range comparator is configured to compare a voltage present on a first I/O pad included in the plurality of I/O pads with a second reference voltage. Advantageously, IO leakage and DC parametric testing may be performed on integrated circuits with high I/O pad counts using an ATE system with a significantly lower quantity of ATE test channels relative to prior approaches.

First claim

What is claimed is:

1. An integrated circuit, comprising:
a plurality of input/output (I/O) pad groups, wherein each I/O pad group comprises:
an on-chip star network;
a plurality of I/O pads;
a plurality of test multiplexers, wherein each test multiplexer included in the plurality of test multiplexers couples a different I/O pad to the on-chip star network;
a digital-to-analog converter (DAC) configured to supply at least one of a source current, a sink current, and a first reference voltage to the on-chip star network; and
a wide-range comparator configured to compare a voltage present on a selected I/O pad included in the plurality of I/O pads with a second reference voltage, wherein a first test multiplexer included in the plurality of test multiplexers couples to a first I/O pad included in the plurality of I/O pads and further couples the wide-range comparator to the on-chip star network.

2. The integrated circuit of claim 1 , wherein each I/O pad included in the plurality of I/O pads is associated with a different receiver included in a plurality of receivers and a different transmitter included in a plurality of transmitters.

3. The integrated circuit of claim 1 , wherein the digital-to-analog converter (DAC) comprises:
a first field-effect transistor (FET) disposed between a voltage source and a first junction; and
a second FET disposed between the first junction and ground,
wherein the first FET and the second FET are operable to supply the at least one of a source current, a sink current, and a first reference voltage to the on-chip star network.

4. The integrated circuit of claim 3 , wherein the DAC further comprises a multiplexer configured to couple the first junction to the on-chip star network.

5. The integrated circuit of claim 3 , wherein, when the DAC is configured to supply the source current, the second FET is configured to be in an off-state, and the first FET is configured to supply the source current to the on-chip star network.

6. The integrated circuit of claim 3 , wherein, when the DAC is configured to supply the sink current, the first FET is configured to be in an off-state, and the second FET is configured to supply the sink current to the on-chip star network.

7. The integrated circuit of claim 3 , wherein, when the DAC is configured to supply the first reference voltage, the first FET and the second FET form a voltage divider that supplies the source current to the on-chip star network.

8. The integrated circuit of claim 1 , wherein the wide-range comparator comprises a differential amplifier with a first input coupled to the selected I/O pad and a second input coupled to the second reference voltage.

9. The integrated circuit of claim 8 , wherein the wide-range comparator further comprises a voltage divider configured to supply the reference voltage to the second input.

10. The integrated circuit of claim 8 , wherein the wide-range comparator further comprises a multiplexer that is configured to couple the first input to the selected I/O pad.

11. A method for testing an integrated circuit that includes an on-chip star network, the method comprising:
causing each test multiplexer included in a plurality of test multiplexers located on the integrated circuit to couple a different input/output (I/O) pad of the integrated circuit to the on-chip star network;
causing a digital-to-analog converter (DAC) located on the integrated circuit to supply at least one of a source current, a sink current, and a first reference voltage to the on-chip star network; and
causing a wide-range comparator located on the integrated circuit to compare a voltage present on a selected I/O pad with a second reference voltage, wherein a first test multiplexer included in the plurality of test multiplexers couples to a first I/O pad included in the plurality of I/O pads and further couples the wide-range comparator to the on-chip star network.

12. The method of claim 11 , wherein the first I/O pad is included in a plurality of I/O pads, and each test multiplexer is configured to couple a different I/O pad included in a plurality of I/O pads to the on-chip star network.

13. The method of claim 12 , wherein each I/O pad included in the plurality of I/O pads is associated with a different receiver included in a plurality of receivers and a different transmitter included in a plurality of transmitters.

14. The method of claim 12 , further comprising:
causing the first test multiplexer to isolate the first I/O pad from the on-chip star network; and
causing a second test multiplexer included in the plurality of test multiplexers to couple a second input/output (I/O) pad included in the plurality of I/O pads to the on-chip star network.

15. The method of claim 11 , wherein causing the DAC located on the integrated circuit to supply at least one of a source current, a sink current, and a first reference voltage to the on-chip star network comprises causing a multiplexer associated with the DAC to couple the DAC to the on-chip star network.

16. A non-transitory computer-readable storage medium including instructions that, when executed by a processor, cause the processor to test an integrated circuit that includes an on-chip star network, by performing the steps of:
causing each test multiplexer included in a plurality of test multiplexers located on the integrated circuit to couple a different input/output (I/O) pad of the integrated circuit to the on-chip star network;
causing a digital-to-analog converter (DAC) located on the integrated circuit to supply at least one of a source current, a sink current, and a first reference voltage to the on-chip star network; and
causing a wide-range comparator located on the integrated circuit to compare a voltage present on a selected I/O pad with a second reference voltage, wherein a first test multiplexer included in the plurality of test multiplexers couples to a first I/O pad included in the plurality of I/O pads and further couples the wide-range comparator to the on-chip star network.

17. The non-transitory computer-readable storage medium of claim 16 , wherein the first I/O pad is included in a plurality of I/O pads, and each test multiplexer is configured to couple a different I/O pad included in a plurality of I/O pads to the on-chip star network.

18. The non-transitory computer-readable storage medium of claim 17 , wherein each I/O pad included in the plurality of I/O pads is associated with a different receiver included in a plurality of receivers and a different transmitter included in a plurality of transmitters.

19. The non-transitory computer-readable storage medium of claim 17 , further including instructions that, when executed by a processor, cause the processor to perform the steps of:
causing the first test multiplexer to isolate the first I/O pad from the on-chip star network; and
causing a second test multiplexer included in the plurality of test multiplexers to couple a second input/output (I/O) pad included in the plurality of I/O pads to the on-chip star network.

20. The non-transitory computer-readable storage medium of claim 16 , wherein causing the DAC located on the integrated circuit to supply at least one of a source current, a sink current, and a first reference voltage to the on-chip star network comprises causing a multiplexer associated with the DAC to couple the DAC to the on-chip star network.

Assignees

• Nvidia Corp

Inventors

• Shaikh Ashfaq
• Lo Wen-Hung
• Kishore Punit
• Sanghani Amit
• RAJAN Krishna

Classifications

• G01R31/2834 Primary

  Automated test systems [ATE]; using microprocessors or computers (G01R31/317 takes precedence; ATE for detection of defective computer hardware G06F11/2736) · CPC title

• G01R31/2884

  using dedicated test connectors, test elements or test circuits on the IC under test (G01R31/2855 takes precedence) · CPC title

• G01R31/2853

  Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections (G01R31/31717 takes precedence; test of chip-to-PCB or lead-to-PCB connections G01R31/66) · CPC title