Input/output cell, integrated circuit device and methods of providing on-chip test functionality

Patent metadata

Field	Value
Publication number	US-9759765-B2
Application number	US-201414288510-A
Country	US
Kind code	B2
Filing date	May 28, 2014
Priority date	May 28, 2014
Publication date	Sep 12, 2017
Grant date	Sep 12, 2017

Abstract

An I/O cell comprising a first set of driver stages comprising, each driver stage of the first set comprising a high side switch controllable to couple an I/O node of the I/O cell to a first high voltage supply node and a low side switch controllable to couple the I/O node of the I/O cell to a first low voltage supply node. The I/O cell further comprising a second set of driver stages, each driver stage of the second set comprising a high side switch controllable to couple the I/O node of the I/O cell to a second high voltage supply node and a low side switch controllable to couple the I/O node of the I/O cell to a second low voltage supply node. The switches of the first set of driver stages are controllable independently of the switches of the second set of driver stages.

First claim

The invention claimed is:

1. An input/output cell for performing on-chip testing within an integrated circuit device comprising:
a first set of driver stages comprising at least one driver stage; each driver stage of the first set comprising a high side switch controllable to couple an input/output node of the input/output cell to a first high voltage supply node and a low side switch controllable to couple the input/output node of the input/output cell to a first low voltage supply node; and
a second set of driver stages comprising at least one driver stage; each driver stage of the second set comprising a high side switch controllable to couple the input/output node of the input/output cell to a second high voltage supply node and a low side switch controllable to couple the input/output node of the input/output cell to a second low voltage supply node; and
the high side and low side switches of the first set of driver stages being controllable independently of the high side and low side switches of the second set of driver stages.

2. The input/output cell of claim 1 , wherein the input/output cell further comprises at least a first switching element operably coupled between the input/output node of the input/output cell and an input/output node of at least one adjacent input/output cell.

3. The input/output cell of claim 1 , wherein the input/output cell further comprises at least a second switching element operably coupled between the input/output node of the input/output cell and at least one on-chip test resource.

4. An integrated circuit device comprising at least one input/output cell according to claim 1 .

5. The integrated circuit device of claim 4 , wherein the integrated circuit device comprises a plurality of input/output cells, wherein:
the input/output node of each input/output cell is operably coupled to a respective input/output pad;
the first high voltage supply nodes of the input/output cells are operably coupled to at least a first high voltage supply pad of the integrated circuit device;
the second high voltage supply nodes of the input/output cells are operably coupled to at least a second high voltage supply pad of the integrated circuit device;
the first low voltage supply nodes of the input/output cells are operably coupled to at least a first low voltage supply pad of the integrated circuit device; and
the second low voltage supply nodes of the input/output cells are operably coupled to at least a second low voltage supply pad of the integrated circuit device.

6. The integrated circuit device of claim 4 , wherein the integrated circuit device comprises at least one on-chip test resource operably coupled to the input/output node of the at least one input/output cell via the at least second switching element and arranged to perform a high output voltage drive strength test.

7. The integrated circuit device of claim 6 , wherein the at least one on-chip test resource is arranged to:
switch on the high side switches in the first and second sets of driver stages within the at least one input/output cell;
switch off the at least one low side switch in the first set of driver stages within the at least one input/output cell;
configure the at least one low side switch in the second set of driver stages within the at least one input/output cell to provide a load between the input/output node of the input/output cell and the second low voltage supply node;
operably couple a current sink to the second low voltage supply node; and
detect a voltage level at at least one of the input/output node of the at least one input/output cell and the second low voltage supply node.

8. The integrated circuit device of claim 6 , wherein the at least one on-chip test resource is arranged to:
switch on the low side switches in the first and second sets of driver stages within the at least one input/output cell;
switch off the at least one high side switch in the first set of driver stages within the at least one input/output cell;
configure the at least one high side switch in the second set of driver stages within the at least one input/output cell to provide a load between the input/output node of the input/output cell and the second high voltage supply node;
operably couple a current source to the second high voltage supply node; and
detect a voltage level at at least one of the input/output node of the at least one input/output cell and the second high voltage supply node.

9. The integrated circuit device of claim 4 , wherein the integrated circuit device comprises at least one on-chip test resource operably coupled to the input/output node of the at least one input/output cell via the at least second switching element and arranged to detect leakage current at the input/output node of the at least one input/output cell.

10. The integrated circuit device of claim 9 , wherein the at least one on-chip test resource is arranged to:
operably couple one of a current sink and a current source to an input node of the at least one on-chip test resource;
configure the at least second switching element of the at least one input/output cell to decouple the input/output node of the at least one input/output cell from the input node of the at least one on-chip test resource;
detect a voltage level at the input node of the at least one on-chip test resource;
configure the at least second switching element of the at least one input/output cell to operably couple the input/output node of the at least one input/output cell to the input node of the at least one on-chip test resource; and
detect a voltage level at the input node of the at least one on-chip test resource.

11. A method of providing on-chip test functionality for a plurality of input/output cells within an integrated circuit device, each input/output cell comprising:
a first set of driver stages comprising at least one driver stage; each driver stage of the first set comprising a high side switch controllable to couple an input/output node of the input/output cell to a first high voltage supply node and a low side switch controllable to couple the input/output node of the input/output cell to a first low voltage supply node;
a second set of driver stages comprising at least one driver stage; each driver stage of the second set comprising a high side switch controllable to couple the input/output node of the input/output cell to a second high voltage supply node and a low side switch controllable to couple the input/output node of the input/output cell to a second low voltage supply node; and
at least one switching element operably coupled between the input/output node of the input/output cell and an input/output node of at least one adjacent input/output cell,
wherein the method comprises:
configuring the switching elements into a closed configuration to operably couple together input/output nodes of adjacent input/output cells such that the input/output nodes of the input/output cells are operably coupled in a chain;
measuring at least one input/output characteristic at an input/output pad operably coupled to an input/output node of one of the input/output cells within the chain of input/output cells; and
iteratively configuring a switching element within an input/output cell at an end of the chain of input/output cells to decouple the input/output node of the input/output cell at the end of the chain and re-measuring the at least one input/output characteristic at the input/output node of the one of the input/output cells within the chain of input/output cells upon each decoupling of an input/output node of an input/output cell at the end of the chain.

Assignees

• Gorman Alistair James
• Culshaw Carl
• Kruecken Josef Maria Joachim
• Nxp Usa Inc

Inventors

• Gorman Alistair James
• Culshaw Carl
• Kruecken Josef Maria Joachim

Classifications

• G01R31/31715

  Testing of input or output circuits; test of circuitry between the I/C pins and the functional core, e.g. testing of input or output driver, receiver, buffer · CPC title

• H03K2217/0072

  Low side switches, i.e. the lower potential [DC] or neutral wire [AC] being directly connected to the switch and not via the load · CPC title

• G01R31/2856 Primary

  Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM] · CPC title

• H03K17/687

  the devices being field-effect transistors · CPC title

• H03K2217/0063

  High side switches, i.e. the higher potential [DC] or life wire [AC] being directly connected to the switch and not via the load · CPC title