Encapsulated microbattery having terminal connected to active layer through a via

Patent metadata

Field	Value
Publication number	US-10236480-B2
Application number	US-201816031099-A
Country	US
Kind code	B2
Filing date	Jul 10, 2018
Priority date	Sep 8, 2016
Publication date	Mar 19, 2019
Grant date	Mar 19, 2019

Abstract

Disclosed herein is an electronic device including a substrate, with an active layer stack on the substrate. A cover is on the active layer stack and has a surface area greater than that of the active layer so as to encapsulate the active layer stack. A conductive pad layer is on the cover. At least one conductive via extends between the active layer stack and the conductive pad layer.

First claim

The invention claimed is:

1. An electronic device, comprising:
a first battery structure comprising:
a first substrate; and
a first active layer stack on the first substrate; and

a second battery structure comprising:
a second active layer stack;

an interstack insulating layer between the first battery structure and the second battery structure; and
at least one interstack conductive via extending from the first active layer stack through the first substrate and through the interstack insulating layer to the second active layer stack.

2. The electronic device of claim 1 , wherein the at least one interstack conductive via comprises an outer insulating layer extending between the first active layer stack and the second active layer stack.

3. The electronic device of claim 1 , wherein the at least one interstack conductive via comprises a plurality of conductive microvias.

4. The electronic device of claim 3 , wherein a diameter of each of the plurality of conductive microvias is less than 200 μm.

5. The electronic device of claim 1 , wherein the second battery structure further comprises a first adhesive layer on the second active layer stack, a metal layer on the first adhesive layer, and a second adhesive layer on the metal layer.

6. The electronic device of claim 1 , further comprising an encapsulating cover over the first active layer stack, wherein the encapsulating cover has a surface area greater than a surface area of the first active layer stack.

7. The electronic device of claim 6 , wherein the encapsulating cover comprises a pre-formed cover stack.

8. An electronic device, comprising:
a first battery structure comprising:
a first substrate;
a first active layer stack on the first substrate and having at least one first electrode area;
a cover on the first active layer stack and having a surface area greater than a surface area of the first active layer stack so as to encapsulate the first active layer stack;
a first conductive pad layer on the cover; and
at least one first conductive via extending between the at least one first electrode area of the first active layer stack and the first conductive pad layer.

9. The electronic device of claim 8 , further comprising:
a second battery structure stacked on the first battery structure and comprising:
a second active layer stack having at least one second electrode area; and
at least one second conductive via extending between the at least one second electrode area and the at least one first electrode area.

10. The electronic device of claim 9 , wherein the at least one second conductive via comprises a plurality of microvias extending between the at least one second electrode area and the at least one first electrode area.

11. The electronic device of claim 10 , wherein each of the plurality of microvias comprises:
a plurality of passageways;
an outer insulating layer within the plurality of passageways; and
an inner conductive layer within the outer insulating layer.

12. The electronic device of claim 10 , wherein each of the plurality of microvias has a diameter of less than 200 μm.

13. The electronic device of claim 9 , wherein the at least one second conductive via of the second battery structure comprises an outer insulating layer extending between the at least one second electrode area and the at least one first electrode area, and an inner conductive layer within the outer insulating layer of the second battery structure and extending between the at least one second electrode area and the at least one first electrode area.

14. The electronic device of claim 9 , further comprising:
a third battery structure stacked on the second battery structure and comprising:
a third active layer stack having at least one third electrode area; and
at least one third conductive via extending between the at least one third electrode area and the at least one second electrode area.

15. The electronic device of claim 14 , wherein the at least one third conductive via of the third battery structure comprises a plurality of microvias extending between the at least one third electrode area and the at least one second electrode area.

16. The electronic device of claim 15 , wherein each of the plurality of microvias comprises:
a plurality of passageways;
an outer insulating layer within the plurality of passageways; and
an inner conductive layer within the outer insulating layer.

17. The electronic device of claim 15 , wherein each of the plurality of microvias has a diameter of less than 200 μm.

18. The electronic device of claim 14 , wherein the at least one third conductive via of the third battery structure comprises an outer insulating layer extending between the at least one third electrode area and the at least one second electrode area, and an inner conductive layer within the outer insulating layer.

Assignees

• St Microelectronics Tours Sas

Inventors

• Fallourd Ludovic

Classifications

• H01M10/0436 Primary

  Small-sized flat cells or batteries for portable equipment · CPC title

• H01M2220/30

  Batteries in portable systems, e.g. mobile phone, laptop · CPC title

• H01M10/044 Primary

  with bipolar electrodes · CPC title

• H01M50/174

  adapted for the shape of the cells · CPC title

• H01M50/55

  on the same side of the cell · CPC title