Semiconductor chip and method for forming a chip pad

Patent metadata

Field	Value
Publication number	US-10236265-B2
Application number	US-201414444874-A
Country	US
Kind code	B2
Filing date	Jul 28, 2014
Priority date	Jul 28, 2014
Publication date	Mar 19, 2019
Grant date	Mar 19, 2019

Abstract

A semiconductor chip with different chip pads and a method for forming a semiconductor chip with different chip pads are disclosed. In some embodiments, the method comprises depositing a barrier layer over a chip front side, depositing a copper layer after depositing the barrier layer, and removing a part of the copper layer located outside a first chip pad region, wherein a remaining portion of the copper layer within the first chip pad region forms a surface layer of the chip pad. The method further comprises removing a part of the barrier layer located outside the first chip pad region.

First claim

What is claimed is:

1. A method for forming a chip, the method comprising:
depositing a barrier layer over a chip front side, the chip front side comprising a first electrical contact and a second electrical contact;
depositing a copper layer after depositing the barrier layer;
removing a part of the copper layer located outside a first chip pad region, wherein a remaining portion of the copper layer within the first chip pad region forms a top most metal surface layer of first chip pad region; and
removing a part of the barrier layer located outside the first chip pad region, wherein the first chip pad region includes the first electrical contact, the barrier layer and the copper layer disposed thereon, and wherein an electrically conductive material of the second electrical contact forms a top most electrically conductive surface layer of a second chip pad region.

2. The method according to claim 1 , wherein the barrier layer is a titanium tungsten layer with a tungsten content ranging from 60% to 90%.

3. The method according to claim 2 , wherein the titanium tungsten layer comprises an average thickness between 20 nm to 200 nm.

4. The method according to claim 1 , wherein the copper layer comprises an average copper content greater than 50%.

5. The method according to claim 1 , wherein removing the part of the copper layer located outside the first chip pad region is implemented by etching the copper layer with a first etching agent, and wherein removing the part of the barrier layer located outside the first chip pad region is implemented by etching the barrier layer with a second etching agent.

6. The method according to claim 5 , wherein etching the part of the copper layer located outside the first chip pad region with the first etching agent uncovers the barrier layer outside the first chip pad region, and wherein the barrier layer functions as an etch stop layer against the first etching agent.

7. The method according to claim 5 , wherein the second etching agent comprises hydrogen peroxide.

8. The method according to claim 1 , further comprising applying a non-oxidizing plasma to the chip front side before depositing the barrier layer over the chip front side.

9. The method according to claim 1 , wherein removing the part of the copper layer and the part of the barrier layer located outside the first chip pad region exposes the second chip pad region comprising the top most electrically conductive surface layer, and wherein the top most electrically conductive surface layer comprises predominantly aluminum.

10. The method according to claim 9 , further comprising applying an oxygen plasma to the top most electrically conductive surface layer of the second chip pad region.

11. The method according to claim 10 , further comprising joining a bond wire to the top most electrically conductive surface layer of the second chip pad region.

12. The method according to claim 1 , further comprising melting a soldering material and a part of the copper layer within the first chip pad region to solder the first chip pad region to an external structure.

13. The method according to claim 1 , wherein the barrier layer and the copper layer are deposited over the whole chip front side.

14. The method according to claim 1 , further comprising forming a solder material in contact with the top most metal surface layer of the first chip pad region.

15. The method according to claim 1 , wherein the copper layer has an average thickness ranging from 0.5 μm to 50 μm.

16. The method according to claim 1 , wherein the barrier layer is directly deposited on the entire chip front side, wherein the copper layer is directly deposited on the entire barrier layer, and wherein the first electrical contact comprises a predominantly aluminum surface and the second electrical contact comprises a predominantly aluminum surface.

17. The method according to claim 16 , wherein the barrier layer consists essentially of titanium tungsten.

18. The method according to claim 16 , further comprising attaching a bond wire to the top most electrically conductive surface layer of the second chip pad region and soldering a solder material to the top most metal surface layer of the first chip pad region to solder the first chip pad region to an external structure.

Assignees

• Infineon Technologies Ag

Inventors

• Kramp Stefan
• Koitz Marco

Classifications

• H10W72/5524

  comprising aluminium [Al] · CPC title

• H10W72/5522

  comprising gold [Au] · CPC title

• H10W72/9415

  relative to the surface, e.g. recessed, protruding · CPC title

• H10W72/5525

  comprising copper [Cu] · CPC title

• H10W72/01971

  Cleaning, e.g. oxide removal · CPC title