Method of offset calibration in a successive approximation register analog-to-digital converter and a successive approximation register analog-to-digital converter

Patent metadata

Field	Value
Publication number	US-10230386-B2
Application number	US-201715835373-A
Country	US
Kind code	B2
Filing date	Dec 7, 2017
Priority date	Dec 8, 2016
Publication date	Mar 12, 2019
Grant date	Mar 12, 2019

Abstract

A method of offset calibration in a SAR ADC is disclosed. In one aspect, the method comprises determining a number of bits of an analog input signal (V IN ), detecting if a binary code determined from the analog input signal (V IN ) matches at least one trigger code, using at least one setting code to determine a calibration bit (B* LSB ; B* MSB ), analyzing a bit of the digital signal (C OUT ) and the calibration bit (B* LSB ; B* MSB ), determining an indication of a presence of offset error, and calibrating the offset error. As the determination of the calibration bit (B* LSB ; B* MSB ) requires only one additional comparison, when compared to the normal operation, the normal operation does not need to be interrupted. Therefore, the calibration can be done in the background and thus can be performed frequently thereby taking into account time-varying changes due to environmental effects.

First claim

What is claimed is:

1. A method of offset calibration in a successive approximation register analog-to-digital converter, SAR ADC, comprising at least one ADC, the method comprising:
determining a number of bits of a digital signal (C OUT ) corresponding to an analog input signal (V IN );
detecting if a binary code determined from the analog input signal (V IN ) matches at least one trigger code;
using at least one setting code corresponding to the at least one trigger code to determine a calibration bit (B* LSB ; B* MSB );
analyzing a bit of the digital signal (C OUT ) with respect to the calibration bit B* LSB ; B* MSB ); and
calibrating for offset error upon determining presence of offset error from the analysis;
wherein analyzing a bit of the digital signal comprises determining the presence of offset error if the bit of the digital signal (C OUT ) is the same as the calibration bit (B* LSB ; B* MSB ).

2. The method according to claim 1 , wherein the at least one ADC comprises a first stage ADC and a second stage ADC, and wherein determining a number of bits of a digital signal comprises:
determining, by the first stage ADC, a number of most significant bits (B MSB ) of the digital signal (C OUT ) corresponding to the analog input signal (V IN );
amplifying, by a gain module, a residue signal (V RES ) output from the first stage ADC; and
determining, by the second stage ADC, a number of least significant bits (B LSB ) of the digital signal (C OUT ) corresponding to the analog input signal (V IN ), and
wherein using at least one setting code further comprises using the at least one setting code corresponding to the at least one trigger code to determine a calibration residue signal (V* RES ) in the first stage ADC.

3. The method according to claim 2 , wherein the calibration residue signal (V* RES ) is determined by calculating a difference between the analog input signal (V IN ) and an analog signal (V* MSB ) representing a part of the at least one setting code.

4. The method according to claim 3 , wherein using at least one setting code further comprises determining the calibration bit (B* LSB ) by comparing an amplified calibration residue signal (V* AMP ) to a further analog signal (V* LSB ) representing a part of the at least one setting code.

5. The method according to claim 1 , wherein analyzing a bit of the digital signal further comprises determining the value of the bit, and, when it has a value of 0, indicating a downwards calibration, and, when it has a value of 1, indicating an upwards calibration.

6. The method according to claim 1 , wherein calibrating for offset error comprises, upon detecting presence of offset error in the at least one ADC, calibrating said at least one ADC by adjusting at least one variable capacitance module in said at least one ADC.

7. The method of offset calibration in a successive approximation register analog-to-digital converter, SAR ADC, comprise at least one ADC, the method comprising:
determining a number of bits of a digital signal (C OUT ) corresponding to an analog input signal (V IN );
detecting if a binary code determined from the analog input signal (V IN ) matches at least one trigger code;
using at least one setting code corresponding to the at least one trigger code to determine a calibration bit (B* LSB ; B* MSB );
analyzing a bit of the digital signal (C OUT ) with respect to the calibration bit (B* LSB ; B* MSB ); and
calibrating for offset error upon determining presence of offset error from the analysis;
wherein using at least one setting code comprises determining the calibration bit (B* MSB ) by comparing the analog input signal (V IN ) to a further analog signal (V* MSB ) representing a part of the at least one setting code.

8. The method according to claim 7 , wherein analyzing a bit of the digital signal further comprises determining the value of the bit, and, when it has a value of 0, indicating a downwards calibration, and, when it has a value of 1, indicating an upwards calibration.

9. The method according to claim 7 , wherein calibrating for offset error comprises, upon detecting presence of offset error in the at least one ADC, calibrating said at least one ADC by adjusting at least one variable capacitance module in said at least one ADC.

10. A method of offset calibration in a successive approximation register analog-to-digital converter, SAR ADC, comprising at least one ADC, the method comprising:
determining a number of bits of a digital signal (C OUT ) corresponding to an analog input signal (V IN );
detecting if a binary code determined from the analog input signal (V IN ) at least one trigger code;
using at least one setting code corresponding to the at least one trigger code to determine a calibration bit (B* LSB ; B* MSB );
analyzing a bit of the digital signal (C OUT ) with respect to the calibration bit (B* LSB ; B* MSB ); and
calibrating for offset error upon determining presence of offset error from the analysis:
wherein the at least one ADC comprises a first stage ADC and a second stage ADC, and
wherein determining a number of bits of a digital signal comprises:
determining, by the first stage ADC, a number of most significant bits (B MSB ) of the digital signal (C OUT ) corresponding to the analog input signal (V IN );
amplifying, by a gain module, a residue signal (V RES ) output from the first stage ADC; and
determining, by the second stage ADC, a number of least significant bits (B LSB ) of the digital signal (C OUT ) corresponding to the analog input signal (V IN );
wherein using at least one setting code further comprises using the at least one setting code corresponding to the at least one trigger code to determine a calibration residue signal (V* RES ) in the first stage ADC.

11. The method according to claim 10 , wherein the calibration residue signal (V* RES ) is determined by calculating a difference between the analog input signal (V IN ) and an analog signal (V* MSB ) representing a part of the at least one setting code.

12. The method according to claim 10 , wherein using at least one setting code further comprises determining the calibration bit (B* LSB ) by comparing an amplified calibration residue signal (V* AMP ) to a further analog signal (V* LSB ) representing a part of the at least one setting code.

13. The method according to claim 10 , wherein using at least one setting code further comprises temporarily storing, in the gain module, the calibration residue signal (V* RES ) until a least significant bit of the digital signal (C OUT ) has been determined.

14. The method according to claim 10 , wherein calibrating for offset error further comprises determining the value of the least significant bit, and, when the value is 1, indicating a downwards calibration, and, when the value is 0, indicating an upwards calibration.

15. The method according to claim 10 , wherein calibrating for offset error comprises, upon detection of presence of offset error in the second stage ADC, calibrating the second stage ADC by adjusting at least one variable capacitance module in the gain module.

16. A successive approximation register analog-to-digital converter, SAR ADC, comprising:
at least one ADC configured to determine a number of hits of a digital signal (C OUT ) corresponding to an analog input signal (V IN ); and
a control module configured to control the at least one ADC and to output the digital output signal (C OUT ) corresponding to the input analog signal (V IN );
wherein the control module is further configured to:
store at least one trigger code;
detect if a bi

Assignees

• Stichting Imec Nederland

Inventors

• Ding Ming
• Li Hanyue
• Harpe Pieter

Classifications

• H03M1/462

  Details of the control circuitry, e.g. of the successive approximation register · CPC title

• H03M1/46

  with digital/analogue converter for supplying reference values to converter · CPC title

• H03M1/1023 Primary

  Offset correction (H03M1/1019 takes precedence; removal of offset already present on the analogue input signal H03M1/1295) · CPC title

• H03M1/1014 Primary

  at one point of the transfer characteristic, i.e. by adjusting a single reference value, e.g. bias or gain error (gain setting for range control H03M1/18) · CPC title

• H03M1/44

  Sequential comparisons in series-connected stages with change in value of analogue signal · CPC title