Data transmission with power supply noise compensation

Patent metadata

Field	Value
Publication number	US-10230370-B2
Application number	US-201715496848-A
Country	US
Kind code	B2
Filing date	Apr 25, 2017
Priority date	Apr 25, 2017
Publication date	Mar 12, 2019
Grant date	Mar 12, 2019

Abstract

In one form, a data transmission system includes transmission and reception circuits. The transmission circuit includes a first driver having an input for receiving a first transmit data signal, an output, a positive power supply terminal for receiving an input/output (I/O) power supply voltage, and a negative terminal for receiving an I/O ground voltage, a second driver having an input for receiving the I/O power supply voltage, an output, and a positive power supply terminal for receiving the I/O power supply voltage, and a third driver having an input for receiving the I/O ground voltage, an output, and a negative power supply terminal coupled to the I/O ground voltage. The reception circuit forms a reference voltage based an average of signal content below a predetermined frequency of outputs of the second and third drivers, and receives a signal from the output of the first driver using the reference voltage.

First claim

What is claimed is:

1. A data transmission system comprising:
a transmission circuit comprising:
a first driver having an input for receiving a first transmit data signal, an output, a positive power supply terminal for receiving an input/output (I/O) power supply voltage, and a negative terminal for receiving an I/O ground voltage;
a second driver having an input for receiving said I/O power supply voltage, an output, and a positive power supply terminal for receiving said I/O power supply voltage, wherein said transmission circuit does not use said second driver during transmission of data; and
a third driver having an input for receiving said I/O ground voltage, an output, and a negative power supply terminal coupled to said I/O ground voltage, wherein said transmission circuit does not use said third driver during transmission of data, and

a reception circuit coupled to said output of said first driver, said output of said second driver, and said output of said third driver, wherein said reception circuit forms a reference voltage based an average of signal content below a predetermined frequency of outputs of said second and third drivers, and receives a signal from said output of said first driver using said reference voltage.

2. The data transmission system of claim 1 , wherein said reception circuit comprises:
a first lowpass filter having an input coupled to said output of said second driver, and an output;
a second lowpass filter having an input coupled to said output of said third driver, and an output; and
an averager having a first input coupled to said output of said first lowpass filter, a second input coupled to said output of said output of said second lowpass filter, and an output for providing said reference voltage.

3. The data transmission system of claim 2 , wherein said reception circuit is formed partially on an integrated circuit chip and said first lowpass filter, said second lowpass filter, and said averager are external to said integrated circuit chip.

4. The data transmission system of claim 2 , wherein said first lowpass filter and said second lowpass filter each have a cutoff frequency above 100 megahertz (MHz).

5. The data transmission system of claim 2 , wherein said reception circuit further comprises:
a variable voltage source having an input coupled to said output of said averager, and an output for providing said reference voltage.

6. The data transmission system of claim 5 , wherein said reception circuit is formed on a single integrated circuit chip.

7. The data transmission system of claim 1 , wherein:
said transmission circuit comprises a plurality of additional drivers each having an input for receiving a corresponding transmit data signal, an output coupled to a corresponding data terminal, a positive power supply terminal for receiving said I/O power supply voltage, and a negative terminal for receiving said I/O ground voltage; and
said reception circuit comprises a plurality of input buffers each having an input coupled to an output terminal of a corresponding driver, an output coupled to a corresponding data terminal, a positive power supply terminal for receiving said I/O power supply voltage, and a negative terminal for receiving said I/O ground voltage.

8. The data transmission system of claim 1 , wherein:
said reception circuit is a double data rate (DDR) DRAM; and
said transmission circuit comprises a double data rate (DDR) dynamic random access memory (DRAM) physical interface circuit, said first driver providing a data output signal, said second driver providing a write clock signal, and said third driver providing an inverse write clock signal.

9. The data transmission system of claim 8 , wherein said reception circuit uses said output of said second driver and said output of said third driver for another purpose.

10. A data transmission system comprising:
a transmission circuit comprising:
a first driver having an input for receiving a first transmit data signal, an output, a positive power supply terminal for receiving an input/output (I/O) power supply voltage, and a negative terminal for receiving an I/O ground voltage; and
a second driver having an input for receiving a clock signal, an output, and a positive power supply terminal for receiving said I/O power supply voltage, and

a reception circuit coupled to said output of said first driver and said output of said second driver, wherein said reception circuit forms a reference voltage based an average of signal content below a predetermined frequency of said output of said second driver, and receives a signal from said output of said first driver using said reference voltage.

11. The data transmission system of claim 10 , wherein said reception circuit comprises:
a lowpass filter having an input coupled to said output of said second driver, and an output; and
a variable voltage source having an input coupled to said output of said lowpass filter, and an output for providing said reference voltage.

12. The data transmission system of claim 10 , wherein:
said transmission circuit comprises a plurality of additional drivers each having an input for receiving a corresponding transmit data signal, an output coupled to a corresponding data terminal, a positive power supply terminal for receiving said I/O power supply voltage, and a negative terminal for receiving said I/O ground voltage; and
said reception circuit comprises a plurality of input buffers each having an input coupled to an output terminal of a corresponding driver, an output coupled to a corresponding data terminal, a positive power supply terminal for receiving said I/O power supply voltage, and a negative terminal for receiving said I/O ground voltage.

13. The data transmission system of claim 10 , wherein said reception circuit uses said output of said second driver for another purpose.

14. The data transmission system of claim 10 , wherein said transmission circuit comprises a double data rate (DDR) dynamic random access memory (DRAM) controller, said first driver provides a data output signal, and said second driver provides a single-ended write clock signal.

15. A data transmission system comprising:
a reference voltage driving circuit comprising:
a first resistor having a first terminal for receiving an input/output (I/O) power supply voltage, and second terminal for coupling to a first end of a first transmission line; and
a second resistor having a first terminal for coupling to a first end of a second transmission line, and a second terminal for receiving an I/O ground voltage,

a first reference voltage forming circuit coupled to a second end of said first transmission line and a second end of said second transmission line, for forming a first reference voltage based an average of signal content below a predetermined frequency of signals at said second ends of said first and second transmission lines; and
a first buffer for receiving a first input signal based on said reference voltage.

16. The data transmission system of claim 15 wherein:
said reference voltage driving circuit, said first transmission line, said second transmission line, and said reference voltage forming circuit are formed on a printed circuit board; and
said first buffer is formed on an integrated circuit.

17. The data transmission system of claim 15 wherein:
said reference voltage driving circuit, said first transmission line, and said second transmission line are formed on a printed circuit board; and
said reference voltage forming circuit and said first buffer and formed on an integrat

Assignees

• Ati Technologies Ulc

Inventors

• Guo Fei
• Frankovich Mark Edward

Classifications

• G05F1/595

  semiconductor devices connected in series · CPC title

• H03K19/00346 Primary

  Modifications for eliminating interference or parasitic voltages or currents · CPC title

• G05F1/562

  with a threshold detection shunting the control path of the final control device · CPC title

• H04B15/02

  Reducing interference from electric apparatus by means located at or near the interfering apparatus · CPC title

• G05F1/571

  with overvoltage detector · CPC title