Semiconductor device and manufacturing method of semiconductor device

Patent metadata

Field	Value
Publication number	US-10229992-B2
Application number	US-201815904701-A
Country	US
Kind code	B2
Filing date	Feb 26, 2018
Priority date	Apr 21, 2017
Publication date	Mar 12, 2019
Grant date	Mar 12, 2019

Abstract

Characteristics of a semiconductor device are improved.
A semiconductor device of the present invention includes a buffer layer composed of a first nitride semiconductor layer, a channel layer composed of a second nitride semiconductor layer, and a barrier layer composed of a third nitride semiconductor layer, which are sequentially laminated, and a cap layer composed of a fourth nitride semiconductor layer of mesa type, which is formed over the barrier layer. The semiconductor device also includes a source electrode formed on one side of the cap layer, a drain electrode formed on the other side of the cap layer, and a first gate electrode formed over the cap layer. The first gate electrode and the cap layer are Schottky-joined. A Schottky gate electrode (the first gate electrode) is provided over the cap layer in this way, so that when a gate voltage is applied, an electric field is applied to the entire cap layer and a depletion layer spreads. Therefore, it is possible to suppress a gate leakage current.

First claim

What is claimed is:

1. A semiconductor device comprising:
a first nitride semiconductor layer;
a second nitride semiconductor layer formed over the first nitride semiconductor layer;
a third nitride semiconductor layer formed over the second nitride semiconductor layer;
a mesa type fourth nitride semiconductor layer formed over the third nitride semiconductor layer;
a source electrode formed over the third nitride semiconductor layer and on one side of the fourth nitride semiconductor layer;
a drain electrode formed over the third nitride semiconductor layer and on the other side of the fourth nitride semiconductor layer; and
a first gate electrode formed over the fourth nitride semiconductor layer,
wherein electron affinity of the second nitride semiconductor layer is greater than or equal to electron affinity of the first nitride semiconductor layer,
wherein electron affinity of the third nitride semiconductor layer is smaller than the electron affinity of the first nitride semiconductor layer,
wherein electron affinity of the fourth nitride semiconductor layer is greater than or equal to the electron affinity of the second nitride semiconductor layer, and
wherein the first gate electrode and the fourth nitride semiconductor layer are Schottky-joined.

2. The semiconductor device according to claim 1 ,
wherein the fourth nitride semiconductor layer is a non-doped layer.

3. The semiconductor device according to claim 2 ,
wherein the fourth nitride semiconductor layer is a non-doped GaN layer.

4. The semiconductor device according to claim 1 ,
wherein the fourth nitride semiconductor layer is a laminated film of a non-doped layer and an n-type layer formed over the non-doped layer.

5. The semiconductor device according to claim 4 ,
wherein the fourth nitride semiconductor layer is a laminated film of a non-doped GaN layer and an n-type GaN layer.

6. The semiconductor device according to claim 1 ,
wherein the fourth nitride semiconductor layer is a laminated film of a p-type layer and a non-doped layer formed over the p-type layer.

7. The semiconductor device according to claim 6 , further comprising:
an n-type layer over the non-doped layer.

8. The semiconductor device according to claim 7 ,
wherein the fourth nitride semiconductor layer is a laminated film of a p-type GaN layer, a non-doped GaN layer, and an n-type GaN layer.

9. The semiconductor device according to claim 1 ,
wherein the fourth nitride semiconductor layer is a laminated film of an n-type layer, a first non-doped layer formed over the n-type layer, a p-type layer formed over the first non-doped layer, and a second non-doped layer formed over the p-type layer.

10. The semiconductor device according to claim 9 ,
wherein the fourth nitride semiconductor layer is a laminated film of an n-type Gan layer, a first non-doped GaN layer, a p-type Gan layer, and a second non-doped Gan layer.

11. The semiconductor device according to claim 1 ,
wherein the fourth nitride semiconductor layer is a laminated film of a non-doped layer and a p-type layer formed over the non-doped layer.

12. The semiconductor device according to claim 11 ,
wherein the fourth nitride semiconductor layer is a laminated film of a non-doped GaN layer and a p-type GaN layer.

13. The semiconductor device according to claim 1 , further comprising:
a first insulating film formed over the third nitride semiconductor layer and the first gate electrode; and
a second gate electrode formed over the first gate electrode through an opening portion of the first insulating film,
wherein the second gate electrode more largely extends toward the source electrode or the drain electrode than the first gate electrode.

14. The semiconductor device according to claim 13 ,
wherein a film thickness of the first insulating film is greater than a film thickness of the fourth nitride semiconductor layer.

15. The semiconductor device according to claim 1 , further comprising:
a first insulating film formed over the third nitride semiconductor layer and the first gate electrode;
a second gate electrode formed over the first gate electrode through a first opening portion of the first insulating film;
a second insulating film formed over the second gate electrode and the first insulating film, and
a third gate electrode formed over the second gate electrode through a second opening portion of the second insulating film.

16. The semiconductor device according to claim 15 ,
wherein the third gate electrode more largely extends toward the source electrode or the drain electrode than the first gate electrode.

17. A manufacturing method of a semiconductor device, the manufacturing method comprising the steps of:
(a) forming a second nitride semiconductor layer over a first nitride semiconductor layer;
(b) forming a third nitride semiconductor layer over the second nitride semiconductor layer;
(c) forming a fourth nitride semiconductor layer over the third nitride semiconductor layer;
(b) forming a first conductive film that is Schottky-joined with the fourth nitride semiconductor layer over the fourth nitride semiconductor layer; and
(e) forming a laminated body of the fourth nitride semiconductor layer of mesa type and a first gate electrode by processing the fourth nitride semiconductor layer and the first conductive film and exposing the third nitride semiconductor layer on both sides of the laminated body,
wherein electron affinity of the second nitride semiconductor layer is greater than or equal to electron affinity of the first nitride semiconductor layer,
wherein electron affinity of the third nitride semiconductor layer is smaller than the electron affinity of the first nitride semiconductor layer, and
wherein electron affinity of the fourth nitride semiconductor layer is greater than or equal to the electron affinity of the second nitride semiconductor layer.

18. The manufacturing method of a semiconductor device according to claim 17 , further comprising the steps of:
(f) forming a first insulating film over the first gate electrode and the third nitride semiconductor layer, and
(g) forming a second gate electrode over the first gate electrode through a first opening portion of the first insulating film.

19. The manufacturing method of a semiconductor device according to claim 17 ,
wherein the step (c) is a step of sequentially forming an n-type layer, a first non-doped layer formed over the n-type layer, a p-type layer formed over the first non-doped layer, and a second non-doped layer formed over the p-type layer as the fourth nitride semiconductor layer.

20. The manufacturing method of a semiconductor device according to claim 18 , further comprising the steps of:
(h) forming a second insulating film over the second gate electrode and the first insulating film, and
(i) forming a third gate electrode over the second gate electrode through a second opening portion of the second insulating film.

Assignees

• Renesas Electronics Corp

Inventors

• Miura Yoshinao
• Miyamoto Hironobu

Classifications

• H10P76/204

  of organic photoresist masks · CPC title

• H10P50/246

  of Group III-V materials · CPC title

• H10P50/71

  using masks for conductive or resistive materials · CPC title

• H10D64/0124

  to Group III-V semiconductors · CPC title

• H10P14/3416

  Nitrides · CPC title