Three plate MIM capacitor via integrity verification

Patent metadata

Field	Value
Publication number	US-10229873-B2
Application number	US-201715426612-A
Country	US
Kind code	B2
Filing date	Feb 7, 2017
Priority date	Feb 7, 2017
Publication date	Mar 12, 2019
Grant date	Mar 12, 2019

Abstract

A three plate MIM capacitor test structure includes a three plate MIM capacitor, a first test wire in a metal layer above/below the three plate MIM, a second test wire below/above the three plate MIM, a third test wire below/above the three plate MIM, a first via connected to the first test wire, a second via connected to a middle plate of the three plate MIM, and a third via connected to the top and bottom plates of the three plate MIM. The test structure may verify the integrity the MIM capacitor by applying a potential to the first test wire, applying ground potential to both the second test wire and the third test wire, and detecting leakage current across the first test wire and the second and third test wires or detecting leakage current across the second test wire and the third test wire.

First claim

The invention claimed is:

1. A method of testing a three plate MIM capacitor test structure comprising:
applying a voltage to a first plate of a three plate MIM capacitor, a second plate of the three plate MIM capacitor, and a third plate of the three plate MIM capacitor;
applying ground potential to a test via that extends through the three plate MIM capacitor;
detecting leakage current across the middle plate and the test via, detecting leakage current across the top plate and the test via, or detecting leakage current across the middle plate and the test via; and
determining there is a short between one of the bottom plate, middle plate, or top plate and the test via caused by a defect of the test via, if leakage current is detected across the middle plate and the test via, if leakage current is detected across the top plate and the test via, or if leakage current is detected across the middle plate and the test via.

2. The method of claim 1 , wherein the test via extends through an associated clearance within each of the bottom plate, middle plate, and top plate.

3. The method of claim 2 , wherein a second via is connected to the middle plate and extends through an associated clearance of the top plate.

4. The method of claim 3 , wherein a third via is connected to both the top plate and the bottom plate and extends through an associated clearance of the middle plate.

5. The method of claim 3 , wherein a first test wire is connected to the test via and is serpentine shaped traversing the three plate MIM capacitor.

6. The method of claim 5 , wherein a second test wire is connected to the second via, wherein a third test wire is connected to the third via, and wherein the second test wire and the third test wire comprises two parallel portions connected by an orthogonal portion.

7. The method of claim 6 , wherein one of the two parallel portions of the third test wire is between the two parallel portions of the second test wire.

8. A three plate MIM capacitor test structure comprising:
a three plate MIM capacitor comprising a bottom plate, a middle plate, and a top plate;
a via matrix normal to the bottom plate, the middle plate, and the top plate, the via matrix comprising: a first via group comprising vias that are configured to not make contact with any of the bottom plate, middle plate, and top plate; a second via group comprising vias that are configured to contact only the middle plate; and a third via group comprising vias that are configured to contact only the top plate and bottom plate;
a first test wire within a wiring level below the three plate MIM capacitor connected to the first via group;
a second test wire within a wiring level above the three plate MIM capacitor connected to the second via group; and
a third test wire within a wiring level above the three plate MIM capacitor connected to the third via group.

9. The three plate MIM capacitor test structure of claim 8 , wherein the vias of the first via group are comprised within a first column of the via matrix, the vias of the second via group are comprised within a second column of the via matrix, and the vias of the third via group are comprised within a third column of the via matrix.

10. The three plate MIM capacitor test structure of claim 8 , wherein the vias of the first via group are comprised within a first row of the via matrix, the vias of the second via group are comprised within a second row of the via matrix, and the vias of the third via group are comprised within a third row of the via matrix.

11. The three plate MIM capacitor test structure of claim 8 , wherein the vias of the first via group are comprised within a first diagonal of the via matrix, the vias of the second via group are comprised within a second diagonal of the via matrix, and the vias of the third via group are comprised within a third diagonal of the via matrix.

12. The three plate MIM capacitor test structure of claim 8 , wherein the vias of the first via group extend through associated clearances within each of the bottom plate, middle plate, and top plate.

13. The three plate MIM capacitor test structure of claim 8 , wherein the vias of the second via group extend through associated clearances within the top plate.

14. The three plate MIM capacitor test structure of claim 8 , wherein the vias of the third via group extend through associated clearances within the middle plate.

15. The three plate MIM capacitor test structure of claim 8 , wherein the first test wire is serpentine shaped.

16. The three plate MIM capacitor test structure of claim 8 , wherein each of the second test wire and third test wire comprises two parallel portions connected by an orthogonal portion.

17. The three plate MIM capacitor test structure of claim 16 , wherein one of the two parallel portions of the third test wire is between the two parallel portions of the second test wire.

18. A design structure tangibly embodied in a machine readable medium for designing, manufacturing, or testing a semiconductor device, the design structure comprising:
a three plate MIM capacitor comprising a bottom plate, a middle plate, and a top plate;
a via matrix normal to the bottom plate, the middle plate, and the top plate, the via matrix comprising: a first via group comprising vias that are configured to not make contact with any of the bottom plate, middle plate, and top plate; a second via group comprising vias that are configured to contact only the middle plate; a third via group comprising vias that are configured to contact only the top plate and bottom plate;
a first test wire within a wiring level below the three plate MIM capacitor connected to the first via group;
a second test wire within a wiring level above the three plate MIM capacitor connected to the second via group; and
a third test wire within a wiring level above the three plate MIM capacitor connected to the third via group.

19. The design structure of claim 18 , wherein the vias of the first via group are comprised within a first column of the via matrix, the vias of the second via group are comprised within a second column of the via matrix, and the vias of the third via group are comprised within a third column of the via matrix.

20. The design structure of claim 18 , wherein the vias of the first via group are comprised within a first diagonal of the via matrix, the vias of the second via group are comprised within a second diagonal of the via matrix, and the vias of the third via group are comprised within a third diagonal of the via matrix.

Assignees

• IBM

Inventors

• Kim Andrew T
• Li Baozhen
• Linder Barry P
• Wu Ernest Y

Classifications

• G01R31/64

  Testing of capacitors · CPC title

• H10P74/277

  Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers · CPC title

• H10P74/273

  Interconnections for measuring or testing, e.g. probe pads · CPC title

• H10P74/207

  Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title