Packaged semiconductor device with tensile stress and method of making a packaged semiconductor device with tensile stress

Patent metadata

Field	Value
Publication number	US-10229870-B2
Application number	US-201213691587-A
Country	US
Kind code	B2
Filing date	Nov 30, 2012
Priority date	Nov 30, 2012
Publication date	Mar 12, 2019
Grant date	Mar 12, 2019

Abstract

An assembled semiconductor device and a method of making an assembled semiconductor device are disclosed. In one embodiment the assembled device includes a carrier having a first thickness, a connection layer disposed on the carrier and a chip disposed on the connection layer, the chip having a second thickness, wherein the second thickness is larger than the first thickness.

First claim

What is claimed is:

1. An assembled device comprising:
a carrier comprising a first thickness;
a connection layer disposed on the carrier; and
a chip disposed on the connection layer, the chip comprising a second thickness,
wherein a ratio x is defined as a ratio between the second thickness and the first thickness, wherein the ratio x fulfills the requirement 1.33≤x≤2, and wherein the carrier is a leadframe wherein a top surface of the chip comprises a tensile stress and a bottom surface of the chip comprises a compressive stress.

2. The assembled device according to claim 1 , wherein the second thickness is equal to or greater than 50 μm and the first thickness is equal to or less than 50 μm.

3. The assembled device according to claim 1 , wherein the second thickness is equal to or greater than 100 μm and the first thickness is equal to or less than 100 μm.

4. The assembled device according to claim 1 , wherein the connection layer comprises a third thickness, the third thickness being between 1 μm and 3 μm.

5. The assembled device according to claim 4 , wherein the connection layer is a diffusion solder layer.

6. The assembled device according to claim 1 , wherein the tensile stress is equal to or greater than 100 MPa.

7. The assembled device according to claim 1 , wherein the ratio x fulfills the requirement 1.66≤x≤2.

8. The assembled device according to claim 1 , wherein the leadframe is a copper leadframe.

9. An assembled device comprising:
a leadframe;
a connection layer disposed on the leadframe; and
a chip comprising a top surface and a bottom surface, the chip being disposed with the bottom surface on the connection layer,
wherein the top surface of the chip comprises a tensile stress and the bottom surface of the chip comprises a compressive stress, and
wherein the tensile stress at the top surface and the compressive stress at the bottom surface is generated by the chip being disposed on the connection layer and the connection layer being disposed on the leadframe.

10. The assembled device according to claim 9 , further comprising:
interconnects connecting chip contact pads with leadframe contact pads; and
an encapsulation encapsulating the leadframe, the connection layer and the chip.

11. The assembled device according to claim 9 , wherein the connection layer comprises a thickness of equal to or less than 20 μm.

12. The assembled device according to claim 9 , wherein the tensile stress is equal to or greater than 100 MPa.

13. The assembled device according to claim 9 , wherein a ratio x is defined as a ratio between a thickness of the chip and a thickness of the leadframe, and wherein the ratio x fulfills the requirement 1.33≤x≤2.

14. The assembled device according to claim 13 , wherein the ratio x fulfills the requirement 1.66≤x≤2.

15. An assembled device comprising:
a leadframe;
a connection layer disposed on the leadframe; and
a chip comprising a top surface and a bottom surface, the chip being disposed with the bottom surface on the connection layer, the chip comprising only a single first source/drain contact at the top surface and only a single second source/drain contact at the top surface,
wherein the chip comprises a tensile stress between the first source/drain contact and the second source/drain contact, wherein the bottom surface of the chip comprises a compressive stress, and
wherein the tensile stress at the top surface and the compressive stress at the bottom surface is generated by the chip being disposed on the connection layer and the connection layer being disposed on the leadframe.

16. The assembled device according to claim 15 , wherein the tensile stress is equal to or greater than wo MPa.

17. The assembled device according to claim 15 , wherein the chip comprises a power semiconductor device.

18. The assembled device according to claim 17 , wherein the connection layer comprises an organic adhesive layer or an inorganic adhesive layer with a thickness of equal to or less than 20 μm.

19. The assembled device according to claim 17 , wherein the connection layer comprises a diffusion solder layer with a thickness of equal to or less than 3 μm.

20. The assembled device according to claim 15 , wherein the connection layer is an organic adhesive or an inorganic adhesive layer.

21. The assembled device according to claim 15 , wherein a ratio x is defined as a ratio between a thickness of the chip and a thickness of the leadframe, and wherein the ratio x fulfills the requirement 1.33≤x≤2.

22. The assembled device according to claim 15 , wherein the tensile stress is equal to or greater than 100 MPa and wherein the compressive stress is equal to or less than −200 MPa.

23. An assembled device comprising:
a carrier comprising a first thickness;
a connection layer disposed on the carrier; and
a chip disposed on the connection layer, the chip comprising a second thickness,
wherein a ratio x is defined as a ratio between the second thickness and the first thickness, wherein the ratio x fulfills the requirement 1.33≤x≤2,
wherein the carrier is a leadframe comprising copper, wherein the chip comprises a substrate including silicon, and wherein the connection layer is a diffusion solder layer.

24. The assembled device according to claim 23 , wherein the second thickness is equal to or greater than 50 μm and the first thickness is equal to or less than 50 μm.

Assignees

• Infineon Technologies Ag

Inventors

• Otremba Ralf

Classifications

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/07541

  Controlling the environment, e.g. atmosphere composition or temperature · CPC title

• H10W72/5524

  comprising aluminium [Al] · CPC title