Three terminal spin hall MRAM

Patent metadata

Field	Value
Publication number	US-10229722-B2
Application number	US-201715666236-A
Country	US
Kind code	B2
Filing date	Aug 1, 2017
Priority date	Aug 1, 2017
Publication date	Mar 12, 2019
Grant date	Mar 12, 2019

Abstract

Improved spin hall MRAM designs are provided that enable writing of all of the bits along a given word line together using a separate spin hall wire for each MTJ. In one aspect, a magnetic memory cell includes: a spin hall wire exclusive to the magnetic memory cell; an MTJ disposed on the spin hall wire, wherein the MTJ includes a fixed magnetic layer separated from a free magnetic layer by a tunnel barrier; and a pair of selection transistors connected to opposite ends of the spin hall wire. An MRAM device and method for operation thereof are also provided.

First claim

What is claimed is:

1. A magnetic memory cell, comprising:
a spin hall wire exclusive to the magnetic memory cell;
a magnetic tunnel junction (MTJ) disposed on the spin hall wire, wherein the MTJ comprises a fixed magnetic layer separated from a free magnetic layer by a tunnel barrier, and wherein the MTJ is an only MTJ disposed on the spin hall wire; and
a pair of selection transistors connected to opposite ends of the spin hall wire, wherein each selection transistor in the pair of selection transistors comprises a source region and a drain region interconnected by a channel region, and a gate configured to regulate charge flow through the channel region, and wherein the source region is connected to an adjacent selection transistor of an adjacent magnetic memory cell.

2. The magnetic memory cell of claim 1 , further comprising:
a magnetic insulating layer in between the MTJ and the spin hall wire.

3. The magnetic memory cell of claim 2 , wherein the magnetic insulating layer comprises nickel oxide.

4. The magnetic memory cell of claim 1 , wherein the fixed magnetic layer and the free magnetic layer each comprises cobalt-iron-boron.

5. The magnetic memory cell of claim 1 , wherein the tunnel barrier comprises magnesium oxide.

6. The magnetic memory cell of claim 1 , wherein the spin hall wire comprises a material selected from the group consisting of: tungsten, tantalum, platinum, bismuth, selenium, and combinations thereof.

7. A magnetic random access memory (MRAM) device, comprising:
bit lines;
word lines oriented orthogonal to the bit lines; and
magnetic memory cells in between the bit lines and word lines, wherein each of the magnetic memory cells comprises: i) a spin hall wire exclusive to the magnetic memory cell, ii) an MTJ disposed on the spin hall wire comprising a fixed magnetic layer separated from a free magnetic layer by a tunnel barrier, wherein the MTJ is an only MTJ disposed on the spin hall wire, and iii) a pair of selection transistors connected to opposite ends of the spin hall wire, wherein each selection transistor in the pair of selection transistors comprises a source region and a drain region interconnected by a channel region, and a gate configured to regulate charge flow through the channel region, wherein the gate is connected to a given one of the word lines with the gates of the selection transistors for a same magnetic memory cell being connected to a same word line.

8. The MRAM device of claim 7 , wherein the drain region of the selection transistor is connected to the spin hall wire.

9. The MRAM device of claim 7 , further comprising:
source lines oriented parallel to the bit lines.

10. The MRAM device of claim 9 , wherein the source region of the selection transistor is connected to one of the source lines.

11. The MRAM device of claim 7 , wherein each of the magnetic memory cells further comprises:
a magnetic insulating layer in between the MTJ and the spin hall wire.

12. The MRAM device of claim 11 , wherein the magnetic insulating layer comprises nickel oxide.

13. A method for operating an MRAM device, the method comprising the steps of:
applying a word line voltage to a given word line of the MRAM device, wherein the MRAM device comprises: bit lines, word lines oriented orthogonal to the bit lines, source lines oriented parallel to the bit lines, and magnetic memory cells in between the bit lines and word lines, wherein each of the magnetic memory cells comprises: i) a spin hall wire exclusive to the magnetic memory cell, ii) an MTJ disposed on the spin hall wire comprising a fixed magnetic layer separated from a free magnetic layer by a tunnel barrier, wherein the MTJ is an only MTJ disposed on the spin hall wire, and iii) a pair of selection transistors connected to opposite ends of the spin hall wire, wherein each selection transistor in the pair of selection transistors comprises a source region and a drain region interconnected by a channel region, and a gate configured to regulate charge flow through the channel region, wherein the gate is connected to a given one of the word lines, wherein the drain region of the selection transistor is connected to the spin hall wire, and wherein the source region of the selection transistor is connected to one of the source lines;
applying a first voltage Vdd to the spin hall wire, via the source lines, in each of the magnetic memory cells to destabilize the free magnetic layer in the MTJ of each of the magnetic memory cells;
applying a write voltage to each of the bit lines corresponding to a logic 1 or a logic 0; and
applying a second voltage Vs to the spin hall wire, via the source lines, in each of the magnetic memory cells, wherein Vs<Vdd,
wherein the step of applying the write voltage to each of the bit lines is performed before the step of applying the second voltage Vs to the spin hall wire.

14. The method of claim 13 , wherein Vs is less than or equal to Vdd/2.

15. The method of claim 13 , wherein a duration d is permitted to pass after the step of applying the write voltage to each of the bit lines is performed before performing the step of applying the second voltage Vs to the spin hall wire, wherein d is from about 0.1 ns to about 5 ns, and ranges therebetween.

16. The method of claim 13 , wherein the write voltage is either 0 volts or Vdd.

17. The method of claim 13 , further comprising the step of:
letting the bit lines float while the first voltage Vdd is applied to the spin hall wire in each of the magnetic memory cells to destabilize the free magnetic layer in the MTJ of each of the magnetic memory cells.

18. The method of claim 13 , further comprising the step of:
applying Vs to the bit lines while the first voltage Vdd is applied to the spin hall wire in each of the magnetic memory cells to destabilize the free magnetic layer in the MTJ of each of the magnetic memory cells.

19. The method of claim 13 , further comprising the steps of:
applying a read voltage to each of the bit lines, while the source lines are grounded; and
comparing current flowing through each of the bit lines to a reference current to determine whether each of the magnetic memory cells stores a logic 1 or a logic 0.

20. The MRAM device of claim 7 , wherein the source region is connected to an adjacent selection transistor of an adjacent magnetic memory cell.

Assignees

• IBM

Inventors

• Debrosse John K
• Sun Jonathan Z
• Worledge Daniel C

Classifications

• G11C2213/82

  Array having, for accessing a cell, a word line, a bit line and a plate or source line receiving different potentials · CPC title

• G11C11/1659

  Cell access · CPC title

• G11C11/18

  using Hall-effect devices · CPC title

• G11C11/1675

  Writing or programming circuits or methods · CPC title

• G11C11/1673

  Reading or sensing circuits or methods · CPC title