Methods of direct cooling of packaged devices and structures formed thereby

Patent metadata

Field	Value
Publication number	US-10228735-B2
Application number	US-201715637439-A
Country	US
Kind code	B2
Filing date	Jun 29, 2017
Priority date	Jun 29, 2017
Publication date	Mar 12, 2019
Grant date	Mar 12, 2019

Abstract

Methods of forming microelectronic package structures/modules, and structures formed thereby, are described. Structures formed herein may include a die disposed on a substrate; a cooling solution comprising a first surface and a second surface opposite the first surface, wherein the second surface is disposed on a backside of the die disposed on a package substrate. A lid comprising an outer surface is disposed on the first surface of the cooling solution, wherein the lid includes a plurality of fins disposed on an inner surface of the lid. A solder is disposed between the outer surface of the lid and the first surface of the cooling solution.

First claim

What is claimed is:

1. A microelectronic package structure comprising:
a die on a substrate;
a cooling solution comprising a first surface and a second surface opposite the first surface, wherein the second surface is on a backside of the die;
a lid comprising an outer surface and an inner surface, wherein the outer surface is on the first surface of the cooling solution, and wherein the lid includes a plurality of fins on the inner surface of the lid; and
a solder between the outer surface of the lid and the first surface of the cooling solution, wherein the solder is on an entire length of the first surface of the cooling solution.

2. The microelectronic package structure of claim 1 wherein the cooling solution comprises an integrated heat spreader.

3. The microelectronic package structure of claim 1 wherein a second die is adjacent the first die on the substrate.

4. The microelectronic package structure of claim 1 wherein the lid comprises a heat sink.

5. The microelectronic package structure of claim 1 wherein the lid comprises an inlet and an outlet port on the outer surface, and wherein the outer surface of the lid is over the entire length of the first surface of the cooling solution.

6. The microelectronic package structure of claim 5 wherein the lid comprises a direct liquid micro jet lid.

7. The microelectronic package structure of claim 6 wherein the plurality of fins comprises a plurality of microchannels.

8. The microelectronic package structure of claim 7 wherein the die comprises an operating power of at least 200 watts.

9. A computing system comprising:
a system board;
a memory connected to the system board;
a package coupled to the memory through the system board, the package including a plurality of die on a substrate, a cooling solution comprising a first surface and a second surface opposite the first surface, wherein the second surface is on a backside of the die;
a lid comprising an outer surface and an inner surface, wherein the outer surface is on the first surface of the cooling solution, and wherein the lid includes a plurality of fins on the inner first surface of the lid; and
a solder directly between the outer surface of the lid and the first surface of the cooling solution, wherein the solder is on an entire length of the first surface of the cooling solution.

10. The computing system of claim 9 wherein the solder comprises a thickness of between 10 to 300 microns.

11. The computing system of claim 9 wherein the thermal conductivity of the solder is greater than 15 W/mK.

12. The computing system of claim 9 wherein the system comprises a server system.

13. The computing system of claim 9 wherein the plurality of fins comprises a plurality of microchannels.

14. The computing system of claim 9 wherein the first surface of the cooling solution is free of a thermal interface material.

15. The computing system of claim 9 wherein the die comprises an operating power of greater than 200 W.

16. The computing system of claim 9 , wherein the substrate is free of a lid retention structure.

17. A method of forming a microelectronic package structure comprising:
providing a cooling solution comprising a first surface and support structures, wherein the support structures are capable of being attached to a package substrate;
providing a lid comprising an outer surface and an inner surface, wherein the lid further comprises a plurality of fins on the inner surface;
forming a solder on an entire length of the first surface of the cooling solution;
attaching the outer surface of the lid to the first surface of the cooling solution; and
attaching a second surface of the cooling solution to a backside of a die.

18. The method of claim 17 wherein the die is on a package substrate, and further comprising attaching the support structures to the package substrate.

19. The method of claim 18 wherein the package substrate comprises a plurality of die.

20. The method of claim 18 wherein a first die and a second die are on the package substrate, and wherein the first die and the second die comprise different heights from each other.

21. The method of claim 18 wherein the package substrate is free of a lid retention mechanism.

22. The method of claim 18 wherein the outer surface of the lid is free of a thermal interface material.

23. The method of claim 18 wherein the lid further comprises an inlet port and an outlet port.

24. The method of claim 23 further comprising flowing a fluid through the inlet and the outlet port of the lid to cool the package structure.

25. The method of claim 17 wherein the lid comprises a direct liquid micro jet lid.

Assignees

• Intel Corp

Inventors

• Kulkarni Devdatta P
• Dischler Richard J
• Chang Je-Young

Classifications

• G06F1/20 Primary

  Cooling means · CPC title

• G06F2200/201

  Cooling arrangements using cooling fluid · CPC title

• H10P14/63

  characterised by the formation processes · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title