Digital-to-analog conversion circuit

Patent metadata

Field	Value
Publication number	US-10224947-B2
Application number	US-201715857651-A
Country	US
Kind code	B2
Filing date	Dec 29, 2017
Priority date	Dec 30, 2016
Publication date	Mar 5, 2019
Grant date	Mar 5, 2019

Abstract

Embodiments of the present invention provide a digital-to-analog conversion circuit, where the digital-to-analog conversion circuit includes a signal amplitude detector and a digital-to-analog converter. When the signal amplitude detector detects a low signal amplitude, a first current module in the digital-to-analog converter operates normally and a second current module in the digital-to-analog converter stops operating. In addition, when stopping operating, the second current module is in a state of a third bias voltage and a fourth bias voltage that are generated by a second bias circuit. When the amplitude detector detects a high signal amplitude subsequently, the second current module resumes normal operation. After operating normally, the second current module switches back to a first bias voltage and a second bias voltage that are generated by a first bias circuit. This reduces a nonlinearity problem caused before a second current module resumes normal operation.

First claim

What is claimed is:

1. A digital-to-analog conversion circuit, comprising a signal amplitude detector and a digital-to-analog converter, wherein the digital-to-analog converter comprises a signal controller, a first current module, and a second current module;
the signal amplitude detector is configured to detect, at a first time T 1 , that a signal amplitude of a digital signal is a low signal amplitude, and send, to the signal controller, first indication information indicating the low signal amplitude, and is further configured to detect, at a second time T 2 after the first time T 1 , that a signal amplitude of the digital signal is a high signal amplitude, and send, to the signal controller, second indication information indicating the high signal amplitude;
the signal controller is configured to receive the first indication information sent by the signal amplitude detector, and generate, according to the first indication information, a first control signal provided to the first current module and generate a second control signal provided to the second current module, wherein the first control signal is used to control a current module that receives the first control signal to operate normally, and the second control signal is used to control a current module that receives the second control signal to stop operating;
the first current module is configured to operate normally according to the first control signal, and set a bias voltage of a gate of a first MOS transistor and a bias voltage of a gate of a second MOS transistor in the first current module respectively to a first bias voltage VBP 1 and a second bias voltage VBN 1 , wherein a source of the first MOS transistor is connected to a first analog power supply VADD, a source of the second MOS transistor is grounded, a drain of the first MOS transistor and a drain of the second MOS transistor are coupled, and the first bias voltage VBP 1 and the second bias voltage VBN 1 are generated by a first bias circuit;
the second current module is configured to stop operating according to the second control signal, and switch a bias voltage of a gate of a third MOS transistor in the second current module from the first bias voltage VBP 1 to a third bias voltage VBP 2 and switch a bias voltage of a gate of a fourth MOS transistor in the second current module from the second bias voltage VBN 1 to a fourth bias voltage VBN 2 , wherein a source of the third MOS transistor is connected to a second analog power supply VADD, a source of the fourth MOS transistor is grounded, a drain of the third MOS transistor and a drain of the fourth MOS transistor are coupled, and the third bias voltage VBP 2 and the fourth bias voltage VBN 2 are generated by a second bias circuit;
the signal controller is further configured to receive the second indication information sent by the signal amplitude detector, and generate, according to the second indication information, the first control signal provided to the second current module; and
the second current module is configured to resume normal operation according to the received first control signal, and switch, after operating normally, the bias voltage of the gate of the third MOS transistor from the third bias voltage VBP 2 to the first bias voltage VBP 1 and switch the bias voltage of the gate of the fourth MOS transistor from the fourth bias voltage VBN 2 to the second bias voltage VBN 1 .

2. The digital-to-analog conversion circuit according to claim 1 , wherein the signal amplitude detector comprises:
a delay module, configured to: receive the digital signal, delay the digital signal for N clock cycles, provide the digital signal that is delayed for the N clock cycles to the signal controller, wherein N is a positive integer greater than or equal to 1, and send the delayed digital signal to a signal amplitude determining circuit after each delay of one clock cycle; and, wherein
the signal amplitude determining circuit is further configured to: determine a maximum signal amplitude value in amplitude values of N delayed digital signals obtained from the delay module, determine, by comparing the maximum signal amplitude value with a preset threshold, that the signal amplitude of the digital signal at the time T 1 is the low signal amplitude and the signal amplitude of the digital signal at the time T 2 is the high signal amplitude, and send the first indication information and the second indication information to the signal controller.

3. The digital-to-analog conversion circuit according to claim 2 , wherein the signal amplitude determining circuit comprises:
a maximum signal amplitude determining circuit, configured to obtain the N delayed digital signals from the delay module, and determine the maximum signal amplitude value in the amplitude values of the N delayed digital signals;
a determining circuit, configured to: compare the maximum signal amplitude value with the preset threshold, and determine that the signal amplitude of the digital signal is the high signal amplitude when the maximum signal amplitude value is greater than the threshold, or determine that the signal amplitude of the digital signal is the low signal amplitude when the maximum signal amplitude value is not greater than the threshold; and
a transmitter circuit, configured to send the first indication information and the second indication information to the signal controller after the determining circuit determines the high signal amplitude and the low signal amplitude.

4. The digital-to-analog conversion circuit according to claim 2 , wherein the signal amplitude determining circuit comprises:
a maximum signal amplitude determining circuit, configured to obtain the N delayed digital signals from the delay module, and determine the maximum signal amplitude value in the amplitude values of the N delayed digital signals;
a determining circuit, configured to: compare the maximum signal amplitude value with the preset threshold, and determine that the signal amplitude of the digital signal is the high signal amplitude when the maximum signal amplitude value is greater than the threshold, or determine that the signal amplitude of the digital signal is the low signal amplitude when the maximum signal amplitude value is not greater than the threshold; and
a transmitter circuit, configured to send the first indication information to the signal controller after the determining circuit determines the high signal amplitude, and send the second indication information to the signal controller after a delay of a preset time period after the determining circuit determines the low signal amplitude.

5. The digital-to-analog conversion circuit according to claim 2 , wherein the delay module comprises N flip-flops, and each flip-flop is configured to execute a delay of one clock cycle.

6. The digital-to-analog conversion circuit according to claim 2 , wherein the second current module comprises a logical conversion unit and a current unit, the current unit comprises the third MOS transistor, the fourth MOS transistor, and three parallel switch branch circuits, the drain of the third MOS transistor and the drain of the fourth MOS transistor are coupled by using the three parallel switch branch circuits, the three parallel switch branch circuits comprise a first switch branch circuit formed by a first SN signal switch and a first SP signal switch connected in series, a second switch branch circuit formed by a second SN signal switch and a second SP signal switch connected in series, and a third switch branch circuit comprising two SZ signal switches connected in series;
the logical conversion unit is configured to receive the first control signal, and generate, based on the first control signal, a switch control signal provided to the current unit, wh

Assignees

• Huawei Tech Co Ltd

Inventors

• Li Ding
• Du Shuai
• Wang Hongpei

Classifications

• H03M1/00

  Analogue/digital conversion; Digital/analogue conversion (conversion of analogue values to or from differential modulation H03M3/00) · CPC title

• H03M1/068 Primary

  the original and additional components or elements being complementary to each other, e.g. CMOS · CPC title

• H03M1/742 Primary

  using current sources as quantisation value generators · CPC title

• H03M1/66

  Digital/analogue converters ({H03M1/001 – } H03M1/10 take precedence) · CPC title

• H03M1/002 Primary

  Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed · CPC title