Digital-to-analog conversion circuit

Patent metadata

Field	Value
Publication number	US-10608653-B2
Application number	US-201916255663-A
Country	US
Kind code	B2
Filing date	Jan 23, 2019
Priority date	Dec 30, 2016
Publication date	Mar 31, 2020
Grant date	Mar 31, 2020

Abstract

Embodiments of the present invention provide a digital-to-analog conversion circuit, where the digital-to-analog conversion circuit includes a signal amplitude detector and a digital-to-analog converter. When the signal amplitude detector detects a low signal amplitude, a first current module in the digital-to-analog converter operates normally and a second current module in the digital-to-analog converter stops operating. In addition, when stopping operating, the second current module is in a state of a third bias voltage and a fourth bias voltage that are generated by a second bias circuit. When the amplitude detector detects a high signal amplitude subsequently, the second current module resumes normal operation. After operating normally, the second current module switches back to a first bias voltage and a second bias voltage that are generated by a first bias circuit. This reduces a nonlinearity problem caused before a second current module resumes normal operation.

First claim

The invention claimed is:

1. A digital-to-analog conversion circuit, comprising:
a first current module and a second current module,
wherein bias voltages of the first current module are a first bias voltage VBP 1 and a second bias voltage VBN 1 , and the first bias voltage VBP 1 and the second bias voltage VBN 1 are generated by a first bias circuit;
wherein one bias voltage of the second current module is switched between the first bias voltage VBP 1 and a third bias voltage VBP 2 , the other bias voltage of the second current module is switched from the second bias voltage VBN 1 and a fourth bias voltage VBN 2 , and the third bias voltage VBP 2 and the fourth bias voltage VBN 2 are generated by a second bias circuit.

2. The digital-to-analog conversion circuit according to claim 1 , wherein the second current module comprises a third MOS transistor and a first voltage switch, and the first voltage switch, coupled to the gate of the third MOS transistor, is configured to select a bias voltage between the first bias voltage VBP 1 and the third bias voltage VBP 2 .

3. The digital-to-analog conversion circuit according to claim 2 , wherein the second current module comprises a fourth MOS transistor and a second voltage switch, and the second voltage switch, coupled to the gate of the fourth MOS transistor, is configured to select a bias voltage between the second bias voltage VBN 1 and the fourth bias voltage VBN 2 .

4. The digital-to-analog conversion circuit according to claim 2 , wherein the second current module comprises three parallel switch branch circuits, the drain of the third MOS transistor and the drain of the fourth MOS transistor are coupled by using the three parallel switch branch circuits, the three parallel switch branch circuits comprise a first switch branch circuit formed by a first SN signal switch and a first SP signal switch connected in series, a second switch branch circuit formed by a second SN signal switch and a second SP signal switch connected in series, and a third switch branch circuit comprising two SZ signal switches connected in series.

5. The digital-to-analog conversion circuit according to claim 4 , wherein a first node between the drain of the third MOS transistor and the three parallel switch branch circuits is connected to a first parasitic capacitor, and a second node between the drain of the fourth MOS transistor and the three parallel switch branch circuits is connected to a second parasitic capacitor.

6. The digital-to-analog conversion circuit according to claim 1 , wherein
a voltage value of the first bias voltage VBP 1 is the same as that of the third bias voltage VBP 2 , and a voltage value of the second bias voltage VBN 1 is the same as that of the fourth bias voltage VBN 2 .

7. The digital-to-analog conversion circuit according to claim 1 , wherein the first current module comprises a first MOS transistor and a third voltage switch, and the third voltage switch, coupled to the gate of the first MOS transistor, is configured to select a bias voltage between the first bias voltage VBP 1 and the third bias voltage VBP 2 .

8. The digital-to-analog conversion circuit according to claim 7 , wherein the first current module comprises a second MOS transistor and a fourth voltage switch, and the fourth voltage switch, coupled to the gate of the second MOS transistor, is configured to select a bias voltage between the second bias voltage VBN 1 and the fourth bias voltage VBN 2 .

9. The digital-to-analog conversion circuit according to claim 1 , wherein the digital-to-analog conversion circuit comprises:
a signal amplitude detector, configured to detect a signal amplitude of an input signal and output a detected result;
wherein the one bias voltage of the second current module is switched between the first bias voltage VBP 1 and the third bias voltage VBP 2 according to the detected result, and the other bias voltage of the second current module is switched from the second bias voltage VBN 1 and the fourth bias voltage VBN 2 according to the detected result.

10. The digital-to-analog conversion circuit according to claim 9 , wherein the signal amplitude detector comprises N flip-flops and a signal amplitude determining circuit,
the N flip-flops coupled to the signal amplitude determining circuit, configured to generate N delayed signals based on the input signal, and provide the N delayed signals to the signal amplitude determining circuit;
the signal amplitude determining circuit, configured to determine the detected result according to the received N delayed signals.

Assignees

• Huawei Tech Co Ltd

Inventors

• Li Ding
• Du Shuai
• Wang Hongpei

Classifications

• H03M1/66

  Digital/analogue converters ({H03M1/001 – } H03M1/10 take precedence) · CPC title

• H03M1/1009

  Calibration · CPC title

• H03M1/002 Primary

  Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed · CPC title

• H03M1/00

  Analogue/digital conversion; Digital/analogue conversion (conversion of analogue values to or from differential modulation H03M3/00) · CPC title

• H03M1/068 Primary

  the original and additional components or elements being complementary to each other, e.g. CMOS · CPC title