Ratioed logic with a high impedance load

Patent metadata

Field	Value
Publication number	US-10224935-B2
Application number	US-201415520698-A
Country	US
Kind code	B2
Filing date	Oct 30, 2014
Priority date	Oct 30, 2014
Publication date	Mar 5, 2019
Grant date	Mar 5, 2019

Abstract

A device having ratioed logic with a high impedance load is described. The device includes a pull-down network coupled between a first voltage and an output. The device also includes a high impedance load coupled between a second voltage and the output. The high impedance load being smaller than a transistor of the pull-down network.

First claim

What is claimed is:

1. A system comprising:
a first voltage;
a second voltage;
an output;
a substrate;
a number of n-channel metal-oxide-semiconductor (NMOS) field effect transistors supported by the substrate and serially-coupled between the first voltage and the output; and
a high impedance load supported by the substrate and serially-coupled between the second voltage and the output,
wherein a first NMOS field effect transistor of the number of NMOS field effect transistors comprises a drain disposed in the substrate, and the high impedance load has an electrode layer disposed on top of the drain of the first NMOS field effect transistor and over the substrate.

2. The system of claim 1 , wherein the number of NMOS field effect transistors include a number of double enclosed NMOS field effect transistors, where a drain of one of the double enclosed NMOS field effect transistors functions as a source of another of the double enclosed NMOS field effect transistors.

3. The system of claim 1 , wherein the high impedance load is a memristor that is non-rewriteable.

4. The system of claim 1 , wherein the first voltage is ground.

5. A method for forming ratioed logic with a high impedance load, comprising:
forming a first metal-oxide-semiconductor field-effect transistor (MOSFET) on a substrate;
forming a second MOSFET on the substrate; and
forming the high impedance load on top of a drain of the second MOSFET,
wherein:
a source of the second MOSFET and a drain of the first MOSFET are shared;
the drain of the first MOSFET is enclosed by a source of the first MOSFET; and
the drain of the second MOSFET is enclosed by the source of the second MOSFET.

6. The method of claim 5 , wherein the high impedance load is a memristor.

7. The method of claim 6 , wherein the memristor is a non-rewriteable memristor.

8. The method of claim 5 , further comprising:
depositing a number of n-type channels in a p-type substrate, wherein the n-type channels correspond to the source and the drain of the first MOSFET and the source and the drain of the second MOSFET; and
forming a first gate of the first MOSFET and a second gate of the second MOSFET.

9. The method of claim 5 , wherein the drain of the second MOSFET is disposed in the substrate, and the high impedance load comprises an electrode layer formed on the drain and over the substrate.

10. A device having ratioed logic, comprising:
an output;
a pull-down network comprising a number of n-channel metal-oxide-semiconductor (NMOS) field-effect transistors serially-coupled between a first voltage and the output;
a high impedance load serially-coupled between a second voltage and the output; and
a substrate, a first NMOS field effect transistor of the number of NMOS field effect transistors comprises a drain disposed in the substrate, and the high impedance load comprises an electrode layer formed on the drain and over the substrate, and wherein a gate of the first NMOS field effect transistor is enclosed by a source of the first NMOS field effect transistor.

11. The device of claim 10 , wherein the high impedance load comprises a memristor in a high resistance state.

12. The device of claim 11 , wherein the memristor is non-rewriteable.

13. The device of claim 10 , wherein the pull-down network and the high impedance load are disposed on a printhead.

14. The device of claim 10 , wherein the electrode layer of the high impedance load is enclosed by the gate of the first NMOS field effect transistor.

15. The device of claim 14 , wherein the drain of the first NMOS field effect transistor is enclosed by the gate of the first NMOS field effect transistor.

16. The device of claim 14 , wherein the source of the first NMOS field effect transistor is enclosed by a gate of a second NMOS field effect transistor of the number of NMOS field effect transistors.

17. A device having ratioed logic, comprising:
an output;
a pull-down network comprising a transistor serially-coupled between a first voltage and the output;
a high impedance load serially-coupled between a second voltage and the output; and
a substrate, the transistor comprising a drain disposed in the substrate, and the high impedance load comprising a first electrode layer formed on the drain and over the substrate, wherein the high impedance load comprises a memory element including the first electrode layer, a second electrode layer, and an insulator layer between the first and second electrode layers.

18. The device of claim 17 , wherein the pull-down network comprises a number of n-channel metal-oxide-semiconductor (NMOS) field-effect transistors.

19. The device of claim 18 , wherein the number of NMOS field effect transistors are formed as a multi-enclosed transistor.

Assignees

• Hewlett Packard Development Co

Inventors

• Ge Ning
• Ng Boon Bing
• Chia Leong Yap

Classifications

• H03K19/18 Primary

  using galvano-magnetic devices, e.g. Hall-effect devices · CPC title

• G11C13/0002

  using resistive RAM [RRAM] elements · CPC title

• H03K19/173

  using elementary logic circuits as components · CPC title

• H03K19/0944

  using MOSFET {or insulated gate field-effect transistors, i.e. IGFET}(H03K19/096 takes precedence) · CPC title

• H03K3/45

  by the use, as active elements, of non-linear magnetic or dielectric devices · CPC title