Semiconductor device and electric power control apparatus

US10224921B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10224921-B2
Application numberUS-201715444876-A
CountryUS
Kind codeB2
Filing dateFeb 28, 2017
Priority dateJul 15, 2015
Publication dateMar 5, 2019
Grant dateMar 5, 2019

How to read this patent

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  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

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  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A driver IC includes a ring-shaped termination area, and a first area and a second area that are respectively arranged outside and inside the termination area on a layout. A sense MOS that is arranged between a floating terminal and a first sense node and is driven at a power supply voltage is formed in the termination area. A fault detection circuit that detects presence of a fault when a voltage of the first sense node is higher than a decision voltage that has been determined in advance in a period of time that a low side driver is driving a low side transistor into an ON state is formed in the first area.

First claim

Opening claim text (preview).

What is claimed is: 1. A semiconductor device comprising: a floating terminal configured to be coupled to a floating voltage source; a first circuit including a low side driver, the first circuit being configured to operate based on a first power supply voltage and a reference voltage; a second circuit including a high side driver, the second circuit being configured to operate based on a second power supply voltage and a voltage of the floating terminal; a first sense MOS transistor coupled between the floating terminal and a first sense node, a gate of the first sense MOS transistor being configured to receive the first power supply voltage; and a fault detection circuit configured to detect that a voltage of the first sense node exceeds a first decision voltage when the low side driver is activated, wherein the first sense MOS transistor clamps the voltage of the first sense node to a predetermined voltage when the voltage of the floating terminal exceeds the predetermined voltage. 2. The semiconductor device according to claim 1 , wherein the first sense MOS transistor is depletion type. 3. The semiconductor device according to claim 1 , wherein the fault detection circuit includes: a filter circuit configured to smooth the voltage of the first sense node; and a first comparator circuit configured to compare an output voltage of the filter circuit with the first decision voltage. 4. The semiconductor device according to claim 1 , wherein the fault detection circuit is further configured to detect that the voltage of the first sense node falls below a second decision voltage when the low side driver is inactivated and the high side driver is activated.

Assignees

Inventors

Classifications

  • between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

  • between laterally-adjacent chips · CPC title

  • changes in structures or sizes · CPC title

  • Plan-view shape, i.e. in top view · CPC title

  • Multiple bond pads having different sizes · CPC title

Patent family

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Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US10224921B2 cover?
A driver IC includes a ring-shaped termination area, and a first area and a second area that are respectively arranged outside and inside the termination area on a layout. A sense MOS that is arranged between a floating terminal and a first sense node and is driven at a power supply voltage is formed in the termination area. A fault detection circuit that detects presence of a fault when a volt…
Who is the assignee on this patent?
Renesas Electronics Corp
What technology area does this patent fall under?
Primary CPC classification H03K17/0822. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Mar 05 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 4 related publications on this page (citations in our corpus or others sharing the same primary CPC).