Solid-state image pickup element and image pickup apparatus

Patent metadata

Field	Value
Publication number	US-10224362-B2
Application number	US-201715633232-A
Country	US
Kind code	B2
Filing date	Jun 26, 2017
Priority date	Mar 29, 2010
Publication date	Mar 5, 2019
Grant date	Mar 5, 2019

Abstract

A solid-state image pickup element including: a photoelectric conversion region; a transistor; an isolation region of a first conductivity type configured to isolate the photoelectric conversion region and the transistor from each other; a well region of the first conductivity type having the photoelectric conversion region, the transistor, and the isolation region of the first conductivity type formed therein; a contact portion configured to supply an electric potential used to fix the well region to a given electric potential; and an impurity region of the first conductivity type formed so as to extend in a depth direction from a surface of the isolation region of the first conductivity type in the isolation region of the first conductivity type between the contact portion and the photoelectric conversion region, and having a sufficiently higher impurity concentration than that of the isolation region of the first conductivity type.

First claim

What is claimed is:

1. An imaging device comprising:
a first pixel unit including a first photoelectric conversion region, a second photoelectric conversion region, and a first floating diffusion region coupled to the first photoelectric conversion region and the second photoelectric conversion region;
a second pixel unit including a third photoelectric conversion region and a fourth photoelectric conversion region, and a second floating diffusion region coupled to the third photoelectric conversion region and the fourth photoelectric conversion region;
in a plan view, a first p-type region and a second p-type region disposed between the first pixel unit and the second pixel unit;
in the plan view, an isolation region disposed between the first p-type region and the second p-type region;
in the plan view, a reset transistor disposed within the isolation region and between the first p-type region and the second p-type region; and
in the plan view, a well contact disposed between the first p-type region and the second p-type region and separated from the reset transistor by the isolation region.

2. The imaging device of claim 1 , further comprising, in the plan view, an amplification transistor and a selection transistor which are disposed between the first pixel unit and the second pixel unit.

3. The imaging device of claim 2 , wherein, in the plan view, the well contact, the amplification transistor and the selection transistor are disposed in a row, in this order.

4. The imaging device of claim 2 , further comprising a first transfer transistor coupled to the first photoelectric conversion region and the first floating diffusion region; and
a second transfer transistor coupled to the third photoelectric conversion region and the second floating diffusion region,
wherein,
at least a portion of the selection transistor is between the first transfer transistor and the second transfer transistor.

5. The imaging device of claim 2 , wherein the amplifier transistor and the reset transistor are connected to a same power source.

6. The imaging device of claim 2 , wherein:
the first photoelectric conversion region and the second photoelectric conversion region are disposed along a first line;
the third photoelectric conversion region and the fourth photoelectric conversion region are disposed along a second line;
the amplification transistor and the selection transistor are disposed along a third line; and
the first line, the second line, and the third line are parallel to each other.

7. The imaging device of claim 2 , wherein, in the plan view, the reset transistor, the amplification transistor, and the selection transistor are disposed in a region where the first pixel unit and the second pixel unit face each other, and the well contact is dispose outside of that region.

8. The imaging device of claim 1 , wherein the first p-type region and the second p-type region are p+-regions.

9. The imaging device of claim 1 , further comprising a p-type conductivity region beneath the isolation region.

10. The imaging device of claim 9 , wherein:
in the plan view, the isolation region is formed on a part of the p-type conductivity region, except for a portion surrounding the well contact, and
the well contact includes a conductive member on a p+-type conductivity region.

11. The imaging device of claim 9 , wherein each of the first p-type region and the second p-type region is a barrier in the p-type conductivity region between said well contact and said first, second, third, and fourth photoelectric conversion regions, each barrier acting against a minority carrier injected from said well contact.

12. The imaging device of claim 11 , wherein said well contact and said reset transistor are disposed without any transistor between them.

13. The imaging device of claim 12 , wherein, in the plan view, the reset transistor is coupled to a power source at a side of the reset transistor that faces the well contact.

14. An electronic device including the imaging device of claim 1 .

Assignees

• Sony Corp

Inventors

• Yamakawa Shinya

Classifications

• H01L27/14603

  Electricity · mapped topic

• H01L27/14636

  Electricity · mapped topic

• H01L27/14689

  Electricity · mapped topic

• H01L27/1463

  Electricity · mapped topic

• H01L27/14634

  Electricity · mapped topic