Method for forming an electrical connection between an electronic chip and a carrier substrate and electronic device

Patent metadata

Field	Value
Publication number	US-10224306-B2
Application number	US-201715602278-A
Country	US
Kind code	B2
Filing date	May 23, 2017
Priority date	Nov 3, 2016
Publication date	Mar 5, 2019
Grant date	Mar 5, 2019

Abstract

An electrical connection wire connects an electrical connection pad of an electrical chip and an electrical connection pad of a carrier substrate to which the electronic chip is mounted. A dielectric layer surrounds at least the bonding wire. The dielectric layer may be a dielectric sheath or a hardened liquid dielectric material. A dielectric material may also cover at least a portion of the electrical chip and carrier substrate. A liquid electrically conductive material is deposited and hardened to form a local conductive shield surrounding the dielectric layer at the bonding wire.

First claim

The invention claimed is:

1. An electronic device, comprising:
a carrier substrate;
an electronic chip mounted on the carrier substrate and including a first electrical connection pad and a second electrical connection pad;
a first electrical connection wire connecting a first electrical connection pad of the carrier substrate and the first electrical connection pad of the electronic chip;
a second electrical connection wire connecting a second electrical connection pad of the carrier substrate and the second electrical connection pad of the electronic chip;
a dielectric layer made of a dielectric material on top of a zone of the electronic chip and of the carrier substrate, the dielectric layer covering the first electrical connection wire and the first electrical connection pads but not covering the second electrical connection wire and the second electrical connection pads, such that the dielectric layer forms a local dielectric coating which completely surrounds the first electrical connection wire and completely covers the first electrical connection pads; and
a local conductive shield made of an electrically conductive material at least partially covering the local dielectric coating and directly contacting the second electrical connection wire and the second electrical connection pads.

2. The electronic device according to claim 1 , wherein the local conductive shield completely covers the local dielectric coating, the second electrical connection wire and the second electrical connection pads.

3. An electronic device, comprising:
a carrier substrate;
an electronic chip mounted on the carrier substrate;
a first electrical connection wire connecting between a first electrical connection pad at the carrier substrate and a second electrical connection pad at the electronic chip;
a second electrical connection wire connecting between a third electrical connection pad at the carrier substrate and a fourth electrical connection pad at the electronic chip;
a dielectric material which completely covers the first electrical connection wire, the first electrical connection pad and the second electrical connection pad but does cover any part of the second electrical connection wire, the third electrical connection pad and the fourth electrical connection pad; and
an electrically conductive material that completely covers said dielectric material and is in physical and electrical contact with at least the second electrical connection wire.

4. The electronic device according to claim 3 , wherein the electrically conductive material further completely covers the second electrical connection wire, the third electrical connection pad and the fourth electrical connection pad.

5. The electronic device according to claim 4 , wherein the dielectric material has a non-uniform thickness along a length of the first electrical connection wire.

6. The device according to claim 1 , wherein the dielectric layer has a non-uniform thickness along a length of the first electrical connection wire.

Assignees

• St Microelectronics Grenoble 2

Inventors

• Auchere David
• Hajji Asma
• Quercia Fabien
• Lopez Jerome

Classifications

• H10W72/07553

  changes in shapes · CPC title

• H10W72/5445

  being orthogonal to a side surface of the chip, e.g. parallel arrangements · CPC title

• H10W72/01515

  Forming coatings · CPC title

• H10W72/583

  Reinforcing structures · CPC title

• H10W72/522

  Multilayered bond wires, e.g. having a coating concentric around a core · CPC title