Sintered solder for fine pitch first-level interconnect (FLI) applications

Patent metadata

Field	Value
Publication number	US-10224299-B2
Application number	US-201615394460-A
Country	US
Kind code	B2
Filing date	Dec 29, 2016
Priority date	Dec 29, 2016
Publication date	Mar 5, 2019
Grant date	Mar 5, 2019

Abstract

Foundation layers and methods of forming a foundation layer are described. Die pads are formed over a die. A dielectric layer is formed over die pads and the die. The dielectric layer is then recessed to expose top portions of the die pads. A first plurality of sintered conductive vias are formed over the die pads. The first sintered conductive vias are coupled to at least one of the die pads. In addition, a photoresist layer may be formed over the dielectric layer and the top portions of the die pads. Via openings are formed in the photoresist layer. A second plurality of sintered conductive vias may then be formed over the first sintered conductive vias to form a plurality of sintered conductive lines. Each of the first and second sintered conductive vias are formed with a liquid phase sintering (LPS) solder paste.

First claim

What is claimed is:

1. A foundation layer, comprising:
a plurality of die pads formed over a silicon die;
a dielectric layer formed over the plurality of die pads and the silicon die, wherein the dielectric layer is recessed to expose top portions of the plurality of die pads; and
a first plurality of sintered conductive vias formed over the plurality of die pads, wherein each of the sintered conductive vias is coupled to at least one of the plurality of die pads, and wherein each of the sintered conductive vias has a deformation to peak load compliance of approximately 0.3 μm/mN.

2. The foundation layer of claim 1 , further comprising:
a photoresist layer formed over the dielectric layer and the top portions of the die pads; and
a plurality of via openings formed in the photoresist layer.

3. The foundation layer of claim 1 , further comprising a second plurality of sintered conductive vias formed over the first plurality of sintered conductive vias to form a plurality of sintered conductive lines.

4. The foundation layer of claim 1 , wherein the dielectric layer comprises a polymer material.

5. The foundation layer of claim 1 , wherein each sintered conductive via is coupled to at least one die pad by the exposed top portion of the die pad formed in the dielectric layer.

6. The foundation layer of claim 3 , wherein each of the first and second sintered conductive vias are formed with a liquid phase sintering (LPS) solder paste.

7. The foundation layer of claim 6 , wherein the LPS solder paste comprises at least one of a sinterable powder and a carrier material.

8. The foundation layer of claim 1 , further comprising a printed circuit board.

9. A foundation layer, comprising:
a first plurality of via openings formed over a first photoresist layer;
a first plurality of sintered conductive vias formed over the first plurality of via openings, wherein each of the first plurality of sintered conductive vias has a deformation to peak load compliance of approximately 0.3 μm/mN;
a second plurality of via openings formed over a second photoresist layer;
a second plurality of sintered conductive vias formed over the second plurality of via openings; and
the second photoresist layer with the second plurality of sintered conductive vias stacked above the first photoresist layer with the first plurality of sintered conductive vias to form a plurality of sintered conductive lines.

10. The foundation layer of claim 9 , wherein each of the sintered conductive lines is coupled to at least one of a plurality of die pads formed over one or more dies.

11. The foundation layer of claim 10 , wherein the plurality of die pads include top portions formed over the plurality of die pads, and wherein each of the sintered conductive lines is coupled to one of the plurality of die pads by the top portions of the plurality of die pads.

12. The foundation layer of claim 9 , wherein each of the sintered conductive vias and the sintered conductive lines are formed with a liquid phase sintering (LPS) solder paste.

13. The foundation layer of claim 9 , wherein the LPS solder paste comprises at least one of a sinterable powder and a carrier material.

14. The foundation layer of claim 9 , further comprising a printed circuit board.

Assignees

• Intel Corp

Inventors

• Oka Mihir A
• Hackenberg Ken P
• Subramanian Vijay Krishnan (Vijay)
• Patel Neha M
• Raravikar Nachiket R

Classifications

• H10W72/29

  Bond pads specially adapted therefor · CPC title

• H10W72/9226

  with via interconnections · CPC title

• H10W72/923

  Bond pads having multiple stacked layers · CPC title

• H10W72/01904

  using temporary auxiliary members, e.g. using sacrificial coatings or handle substrates · CPC title

• H10W72/07236

  Soldering or alloying · CPC title