Directional sio2 etch using plasma pre-treatment and high-temperature etchant deposition
US-2015072508-A1 · Mar 12, 2015 · US
US10224180B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-10224180-B2 |
| Application number | US-201815943208-A |
| Country | US |
| Kind code | B2 |
| Filing date | Apr 2, 2018 |
| Priority date | Oct 4, 2016 |
| Publication date | Mar 5, 2019 |
| Grant date | Mar 5, 2019 |
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Described processing chambers may include a chamber housing at least partially defining an interior region of a semiconductor processing chamber. The chamber may include a showerhead positioned within the chamber housing, and the showerhead may at least partially divide the interior region into a remote region and a processing region in which a substrate can be contained. The chamber may also include an inductively coupled plasma source positioned between the showerhead and the processing region. The inductively coupled plasma source may include a conductive material within a dielectric material.
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The invention claimed is: 1. A semiconductor processing chamber comprising: a chamber housing at least partially defining a processing region of the semiconductor processing chamber; and an inductively coupled plasma source positioned within the chamber housing, wherein the inductively coupled plasma source comprises a conductive material within a dielectric material, and wherein the conductive material comprises a copper tube configured to receive a fluid flowed within the copper tube. 2. The semiconductor processing chamber of claim 1 , wherein the dielectric material is selected from the group consisting of aluminum oxide, yttrium oxide, single crystalline silicon, and quartz. 3. The semiconductor processing chamber of claim 1 , wherein the dielectric material defines apertures through the inductively coupled plasma source, and wherein the conductive material is positioned about the apertures within the dielectric material. 4. The semiconductor processing chamber of claim 3 , wherein the apertures are included in a uniform pattern across the dielectric material and about the conductive material. 5. The semiconductor processing chamber of claim 1 , wherein the conductive material is configured in a planar spiral pattern within the dielectric material. 6. The semiconductor processing chamber of claim 1 , wherein the conductive material is configured in a coil extending vertically within the dielectric material for at least two complete turns of the conductive material. 7. The semiconductor processing chamber of claim 1 , wherein the conductive material comprises two conductive tubes positioned within the inductively coupled source. 8. The semiconductor processing chamber of claim 7 , wherein a first tube is included in a first configuration within the inductively coupled source, wherein a second tube is included in a second configuration within the inductively coupled source, and wherein the second configuration is radially inward of the first configuration. 9. The semiconductor processing chamber of claim 8 , wherein the first configuration and the second configuration are each coiled configurations extending vertically within the dielectric material. 10. The semiconductor processing chamber of claim 8 , wherein the first configuration and the second configuration are each a planar configuration and are coplanar within the inductively coupled source. 11. The semiconductor processing chamber of claim 8 , wherein the first tube and the second tube are coupled with an RF source. 12. The semiconductor processing chamber of claim 11 , wherein the first tube and the second tube are each coupled with the RF source through a capacitive divider. 13. The semiconductor processing chamber of claim 1 , wherein the inductively coupled source comprises at least two plates coupled together, wherein each plate defines at least a portion of a channel, and wherein the conductive material is housed within the channel at least partially defined by each of the at least two plates. 14. An inductively coupled plasma source comprising: a first plate defining at least a portion of a channel within the first plate, wherein the first plate comprises a dielectric material, and wherein the first plate defines apertures through the first plate; and a conductive material seated within the at least a portion of the channel, wherein the conductive material is characterized by a spiral or coil configuration, wherein the conductive material is coupled with an RF source, and wherein a central axis of each aperture is normal to the at least a portion of the channel. 15. The inductively coupled plasma source of claim 14 , wherein the source comprises a thickness of at least three inches. 16. The inductively coupled plasma source of claim 14 , further comprising a second plate coupled with the first plate enclosing the conductive material between the first plate and the second plate, wherein the second plate defines second apertures axially aligned with first apertures defined through the first plate. 17. A semiconductor processing chamber comprising: a chamber housing at least partially defining an interior region of the semiconductor processing chamber, wherein the chamber housing includes a lid assembly including an inlet for receiving precursors into the semiconductor processing chamber; a showerhead positioned within the chamber housing, wherein the showerhead at least partially defines a semiconductor processing region from above; and an inductively coupled plasma source positioned within the semiconductor processing region, wherein the inductively coupled plasma source comprises a conductive material within a dielectric material.
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