Bulk MLCC capacitor module

Patent metadata

Field	Value
Publication number	US-10224149-B2
Application number	US-201615264305-A
Country	US
Kind code	B2
Filing date	Sep 13, 2016
Priority date	Dec 9, 2015
Publication date	Mar 5, 2019
Grant date	Mar 5, 2019

Abstract

Provided is a module comprising a carrier material, comprising a first conductive portion and a second conductive portion, and a multiplicity of electronic components wherein each electronic component comprises a first external termination with at least one first longitudinal edge and a second external termination with at least one second longitudinal edge. A first longitudinal edge of a first electronic component is connected to the first conductive portion by a first interconnect; and a second longitudinal edge of the first electronic component is connected to the second conductive portion by a second interconnect.

First claim

The invention claimed is:

1. A module comprising:
a carrier material comprising a first conductive portion and a second conductive portion;
a multiplicity of electronic components wherein each electronic component of said electronic components comprises a first external termination with at least one first longitudinal edge and a second external termination with at least one second longitudinal edge;
a first electronic component of said multiplicity of electronic components wherein said first longitudinal edge of said first electronic component is connected to said first conductive portion by a first interconnect;
a second electronic component of said multiplicity of electronic components wherein said first longitudinal edge of said second electronic component is connected to said first conductive portion by said first interconnect;
and
said second longitudinal edge of said first electronic component is connected to said second conductive portion by a second interconnect wherein said first longitudinal edge is on a first side face of four side faces of said first electronic component.

2. The module of claim 1 wherein said carrier material is a substrate.

3. The module of claim 2 wherein said substrate comprises a material selected from the group consisting of FR4, ceramic and polyimide.

4. The module of claim 1 wherein said carrier material is selected from the group consisting of a pair of leads of ferrous or non-ferrous material wherein a first lead of said pair of leads is said first conductive portion and a second lead of said pair of leads is said second conductive portion.

5. The module of claim 4 wherein said first conductive portion is a conductive trace on said substrate.

6. The module of claim 5 wherein said conductive trace is linear.

7. The module of claim 5 wherein said conductive trace deviates from linearity.

8. The module of claim 7 comprising electronic components of different sizes connected to said conductive trace.

9. The module of claim 4 wherein said first lead comprises an offset.

10. The module of claim 9 wherein said offset is selected from laterally offset and horizontally offset.

11. The module of claim 4 wherein said first lead is selected from a round lead frame and a flat lead.

12. The module of claim 11 wherein said first lead comprises at least one flattened region.

13. The module of claim 4 wherein said first lead is selected from a through-hole lead, surface mount lead and a compliant pin lead.

14. The module of claim 13 further comprising a through-hole assembly stand-off feature.

15. The module of claim 4 wherein said first lead comprises a material selected from a ferrous material and a non-ferrous material.

16. The module of claim 1 wherein said first longitudinal edge of said second electronic component is connected to said first conductive portion by an additional interconnect.

17. The module of claim 1 wherein a second longitudinal edge of said second electronic component is connected to a first longitudinal edge of a third electronic component by an additional interconnect.

18. The module of claim 1 wherein said multiplicity of electronic components are arranged in rows and columns wherein adjacent electronic components in said columns have adjacent longitudinal edges connected by an additional interconnect.

19. The module of claim 1 wherein at least one of said first interconnect or said second interconnect is selected from the group consisting of a transient liquid phase sintering conductive interconnect material.

20. The module of claim 1 wherein each said electronic component is independently selected from the group consisting of a capacitor, a diode, a resistor, a varistor, an inductor, a fuse and an integrated circuit.

21. The module of claim 20 wherein at least one said electronic component is a capacitor.

22. The module of claim 21 wherein each said electronic component is a capacitor.

23. The module of claim 22 wherein each said capacitor is an MLCC.

24. The module of claim 1 wherein at least two said electronic components have a different size.

25. The module of claim 1 further comprising an encapsulation.

26. The module of claim 1 further comprising an over-molded lead frame or pre-molded housing.

27. The module of claim 1 comprising at least 2 electronic components to no more than 100 electronic components.

28. A module comprising:
a carrier material comprising a first conductive portion and a second conductive portion;
a multiplicity of electronic components wherein each electronic component of said electronic components comprises a first external termination with at least one first longitudinal edge and a second external termination with at least one second longitudinal edge;
a first electronic component of said multiplicity of electronic components wherein said first longitudinal edge of said first electronic component is connected to said first conductive portion by a first interconnect;
a second electronic component of said multiplicity of electronic components wherein said first longitudinal edge of said second electronic component is connected to said first conductive portion by said first interconnect;
and
said second longitudinal edge of said first electronic component is connected to said second conductive portion by a second interconnect;
wherein said carrier material is selected from the group consisting of a pair of leads of ferrous or non-ferrous material wherein a first lead of said pair of leads is said first conductive portion and a second lead of said pair of leads is said second conductive portion; and wherein said first lead is a flat plated lead with at least one said electronic component on each side of said flat plated lead.

29. A method for forming a module comprising:
providing a multiplicity of electronic components wherein each electronic component of said electronic components comprises a first external termination with at least one first longitudinal edge wherein said first longitudinal edge is on a side face of four side faces of each electronic component of said electronic components and a second external termination with at least one second longitudinal edge;
placing a first conductor into contact with each said first longitudinal edge with a first interconnect between said first conductor and said first longitudinal edge;
placing a second conductor into contact with said second longitudinal edge with a second interconnect between said second conductor and said second longitudinal edge; and
heating to form a bond of said first interconnect and said second interconnect.

30. The method for forming a module of claim 29 wherein said first conductor is selected from the group consisting of a first lead and a circuit trace on a substrate.

31. The method for forming a module of claim 30 wherein said first lead comprises an offset.

32. The method for forming a module of claim 31 wherein said offset is selected from laterally offset and horizontally offset.

33. The method for forming a module of claim 30 wherein said first lead is selected from a round lead frame and a flat lead.

34. The method for forming a module of claim 33 wherein said first lead comprises at least one flattened region.

35. T

Assignees

• Kemet Electronics Corp

Inventors

• Miller Galen W
• Mcconnell John E
• Bultitude John
• Renner Garry L

Classifications

• H10W70/611

  for connecting multiple chips together · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

• H10W90/811

  Multiple chips on leadframes · CPC title

• H10W72/00

  Interconnections or connectors in packages · CPC title

• H01G2/06

  specially adapted for mounting on a printed-circuit support · CPC title