Stacked switched capacitor energy buffer circuit

Patent metadata

Field	Value
Publication number	US-10218289-B2
Application number	US-201314360992-A
Country	US
Kind code	B2
Filing date	Jan 17, 2013
Priority date	Jan 17, 2012
Publication date	Feb 26, 2019
Grant date	Feb 26, 2019

Abstract

A stacked switched capacitor (SSC) energy buffer circuit includes a switching network and a plurality of energy storage capacitors. The switching network need operate at only a relatively low switching frequency and can take advantage of soft charging of the energy storage capacitors to reduce loss. Thus, efficiency of the SSC energy buffer circuit can be extremely high compared with the efficiency of other energy buffer circuits. Since circuits utilizing the SSC energy buffer architecture need not utilize electrolytic capacitors, circuits utilizing the SSC energy buffer architecture overcome limitations of energy buffers utilizing electrolytic capacitors. Circuits utilizing the SSC energy buffer architecture (without electrolytic capacitors) can achieve an effective energy density characteristic comparable to energy buffers utilizing electrolytic capacitors. The SSC energy buffer architecture exhibits losses that scale with the amount of energy buffered, such that a relatively high efficiency can be achieved across a desired operating range.

First claim

What is claimed is:

1. A stacked switched capacitor (SSC) energy buffer circuit comprising:
two sub-circuits having terminals that are serially coupled during a first operating mode wherein each sub-circuit comprises one or more capacitors, and at least one sub-circuit further comprises a plurality of switches disposed and operable to selectively couple the one or more capacitors of the at least one sub-circuit to: (a) enable dynamic reconfiguration of how the one or more capacitors of the at least one sub-circuit are coupled to the terminals of the at least one sub-circuit; and (b) dynamically reconfigure one or more interconnections among the one or more capacitors within the at least one sub-circuit; wherein the SSC energy buffer circuit provides a total peak energy buffering capability and wherein the peak energy buffered by one of the two sub-circuits is greater than 66% of the total peak energy buffering capability of the SSC energy buffer circuit.

2. The SSC energy buffer circuit of claim 1 wherein the switches in at least one of the two sub-circuits are arranged to dynamically reconfigure a polarity with which at least one capacitor is connected to the terminals of the sub-circuit.

3. The SSC energy buffer circuit of claim 1 , further comprising a pre-charge circuit coupled to each of the two sub-circuits said pre-charge circuit operable to charge each of the one or more capacitors in the two sub-circuits to specified initial conditions before entering the first operating mode.

4. The SSC energy buffer circuit of claim 1 wherein at least one subcircuit comprises a plurality of sub-sub-circuits connected in parallel, wherein each sub-sub-circuit comprises a switch serially coupled to a capacitor.

5. The SSC energy buffer circuit of claim 1 wherein the one or more capacitors in at least one of the two sub-circuits are of a type that are configured to be charged and discharged over a voltage range within about 72% of a nominal voltage.

6. The SSC energy buffer circuit of claim 1 wherein the one or more capacitors in at least one of the two sub-circuits are provided as: one of film capacitors, ultra capacitors and electrolytic capacitors.

7. The SSC energy buffer circuit of claim 1 further comprising an energy buffer port wherein the plurality of switches of at least one of the two sub-circuits are disposed and operable to selectively couple the one or more capacitors of the at least one of the two sub-circuits to enable dynamic reconfiguration of both the one or more interconnections among the capacitors and their connection to the energy buffer port.

8. The SSC energy buffer circuit of claim 7 wherein the plurality of switches of at least one of the two sub-circuits are disposed and operable to cooperatively operate as a switching network such that a voltage at the energy buffer port varies about 12.5% or less as the capacitors charge and discharge up to a voltage range of about 72% of their peak energy storage rating.

Assignees

• Massachusetts Inst Technology

Inventors

• Perreault David J
• Afridi Khurram K
• Chen Minjie
• Leeb Steven B
• Chang Arthur Hsu Chen

Classifications

• H02J4/25

  for transfer of electric power between AC and DC networks, e.g. for supplying the DC section within a load from an AC mains system · CPC title

• H01G4/38 Primary

  Multiple capacitors, i.e. structural combinations of fixed capacitors · CPC title

• H02J5/00

  Electricity · mapped topic

• H02M7/537 Primary

  using semiconductor devices only, e.g. single switched pulse inverters · CPC title

• Y02T10/7022

  Cross-Sectional Technologies · mapped topic