Enhanced stacked switched capacitor energy buffer circuit

Patent metadata

Field	Value
Publication number	US-9762145-B2
Application number	US-201314362163-A
Country	US
Kind code	B2
Filing date	Jan 17, 2013
Priority date	Jan 17, 2012
Publication date	Sep 12, 2017
Grant date	Sep 12, 2017

Abstract

A stacked switched capacitor (SSC) energy buffer circuit includes a switching network and a plurality of energy storage capacitors. The switching network need operate at only a relatively low switching frequency and can take advantage of soft charging of the energy storage capacitors to reduce loss. Thus, efficiency of the SSC energy buffer circuit can be extremely high compared with the efficiency of other energy buffer circuits. Since circuits utilizing the SSC energy buffer architecture need not utilize electrolytic capacitors, circuits utilizing the SSC energy buffer architecture overcome limitations of energy buffers utilizing electrolytic capacitors. Circuits utilizing the SSC energy buffer architecture (without electrolytic capacitors) can achieve an effective energy density characteristic comparable to energy buffers utilizing electrolytic capacitors. The SSC energy buffer architecture exhibits losses that scale with the amount of energy buffered, such that a relatively high efficiency can be achieved across a desired operating range.

First claim

What is claimed is:

1. A stacked switched capacitor (SSC) energy buffer circuit having a first terminal configured to be coupled to a first reference voltage and a second terminal configured to be coupled to a second reference voltage different from the first reference voltage, the circuit comprising:
two sub-circuits that are serially coupled during a first operating mode wherein each sub-circuit comprises one or more capacitors, and at least one sub-circuit further comprises more than one capacitor and a plurality of switches disposed to selectively couple the capacitors to: (a) enable dynamic reconfiguration of how the capacitors are coupled to the terminals of the sub-circuit; and (b) dynamically reconfigure the interconnection among the capacitors within the sub-circuit.

2. The SSC energy buffer circuit of claim 1 wherein the switches in at least one of the two sub-circuits are arranged to dynamically reconfigure a polarity with which at least one capacitor is connected to the terminals of the sub-circuit.

3. The SSC energy buffer circuit of claim 1 , further comprising a pre-charge circuit coupled to each of the two sub-circuits said pre-charge circuit operable to charge each of the one or more capacitors in the two sub-circuits to specified initial conditions before entering the first operating mode.

4. The SSC energy buffer circuit of claim 1 wherein at least one subcircuit comprises a plurality of sub-sub-circuits connected in parallel, wherein each sub-sub-circuit comprises a switch serially coupled to a capacitor.

5. The SSC energy buffer circuit of claim 1 wherein the peak energy buffered by one of the two sub-circuits is greater than 66% of the total peak energy buffering capability.

6. The SSC energy buffer circuit of claim 1 wherein the capacitors in at least one of the two sub-circuits are of a type that can be charged and discharged over voltage range within about 72% of a nominal voltage.

7. The SSC energy buffer circuit of claim 1 wherein the capacitors in at least one of the first and second blocks are provided as: one of film capacitors, ultra capacitors and electrolytic capacitors.

8. The SSC energy buffer circuit of claim 1 wherein the switches are disposed to selectively couple the capacitors to enable dynamic reconfiguration of both the interconnection among the capacitors and their connection to a buffer port.

9. The SSC energy buffer circuit of claim 1 wherein the switches are enabled to cooperatively operate as a switching network such that the voltage seen at a buffer port varies within about 12.5% of a nominal voltage as the capacitors charge and discharge over a voltage range of up to about 72% of a peak storage capacity of the capacitors to buffer energy.

10. A circuit comprising:
a first set of circuitry comprising:
m capacitors; and
m switches, the number of capacitors and switches being equal and wherein each m switch is serially coupled to a corresponding one of the m capacitors; and

a second set of circuitry comprising:
n and only n capacitors; and
n switches, the number of capacitors and switches being equal and wherein each n switch is serially coupled to a corresponding one of the n capacitors;

wherein a voltage across the first set of circuitry and the second set of circuitry is a bus voltage,
wherein the circuit is configured to maintain the bus voltage within a predetermined range of a nominal value, and
wherein n and m are integers greater than zero.

11. The circuit of claim 10 wherein the first set of circuitry includes an H-bridge switch and wherein said H-bridge switch is disposed to allow at least some of said m capacitors to be charged in a bipolar fashion.

12. The circuit of claim 10 wherein n=2 and m=4, and
wherein the circuit has an energy buffering ratio, γ b of 81.6%.

13. The circuit of claim 10 wherein n=1 and m=3, and
wherein the circuit has an energy buffering ratio of:

Y
b

=

n
⁢

⁢

C
1

⁡

[

(

1
+

2
⁢
m
⁢

⁢

R
v

⁢

C
2

C
1

+

C
2

)

2

-

(

1
-

2
⁢
m
⁢

⁢

R
v

⁢

C
2

C
1

+

C
2

)

2

Assignees

• Perreault David J
• Afridi Khurram K
• Chen Minjie
• Leeb Steven B
• Chang Arthur Hsu Chen
• Massachusetts Inst Technology

Inventors

• Perreault David J
• Afridi Khurram K
• Chen Minjie
• Leeb Steven B
• Chang Arthur Hsu Chen

Classifications

• H02J4/25

  for transfer of electric power between AC and DC networks, e.g. for supplying the DC section within a load from an AC mains system · CPC title

• Y02T10/7022

  Cross-Sectional Technologies · mapped topic

• H01G4/30

  Stacked capacitors (H01G4/33 takes precedence) · CPC title

• H02M7/537 Primary

  using semiconductor devices only, e.g. single switched pulse inverters · CPC title

• H02J5/00

  Electricity · mapped topic