Light emitting diode chip having temperature compensation of the wavelength

US10217896B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10217896-B2
Application numberUS-201515532236-A
CountryUS
Kind codeB2
Filing dateNov 25, 2015
Priority dateDec 1, 2014
Publication dateFeb 26, 2019
Grant dateFeb 26, 2019

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  1. Title

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  2. Abstract

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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Abstract

Official abstract text for this publication.

An optoelectronic semiconductor chip is disclosed. In an embodiment the optoelectronic semiconductor chip includes a p-type semiconductor region, an n-type semiconductor region, and an active layer arranged between the p-type semiconductor region and the n-type semiconductor region. The active layer is designed as a multiple quantum well structure, wherein the multiple quantum well structure has a first region of alternating first quantum well layers and first barrier layers and a second region having at least one second quantum well layer and at least one second barrier layer. The at least one second quantum well layer has an electronic band gap (E QW2 ) that is less than the electronic band gap (E QW1 ) of the first quantum well layers, and the at least one second barrier layer has an electronic band gap (E B2 ) that is greater than the electronic band gap (E B1 ) of the first barrier layers.

First claim

Opening claim text (preview).

The invention claimed is: 1. An optoelectronic semiconductor chip comprising: a p-type semiconductor region; an n-type semiconductor region; an active layer arranged between the p-type semiconductor region and the n-type semiconductor region, wherein the active layer is embodied as a multiple quantum well structure, the multiple quantum well structure comprising: a first region containing alternating first quantum well layers and first barrier layers; and a second region containing at least one second quantum well layer and at least one second barrier layer, wherein the at least one second quantum well layer has an electronic bandgap EQW 2 which is smaller than an electronic bandgap EQW 1 of the first quantum well layers, wherein the at least one second barrier layer has an electronic bandgap EB 2 which is larger than an electronic bandgap EB 1 of the first barrier layers, and wherein the second region is arranged closer to the p-type semiconductor region than is the first region. 2. The optoelectronic semiconductor chip as claimed in claim 1 , wherein, for the electronic bandgaps of the first quantum well layers and of the at least one second quantum well layer, the following equation is true: EQW 1 −EQW 2 ≥0.025 eV. 3. The optoelectronic semiconductor chip as claimed in claim 2 , wherein, for the electronic bandgaps of the first barrier layers and of the at least one second barrier layer, the following equation is true: EB 2 −EB 1 ≥0.075 eV. 4. The optoelectronic semiconductor chip as claimed in claim 1 , wherein the first quantum well layers and the at least one second quantum well layer each contain InxAlyGal-x-yP, InxAlyGal-x-yN or InxAlyGal-x-yAs, where 0≤x≤1, 0≤y≤1 and x+y≤1. 5. The optoelectronic semiconductor chip as claimed in claim 4 , wherein the aluminum content y of the first quantum well layers is greater than the aluminum content y of the at least one second quantum well layer. 6. The optoelectronic semiconductor chip as claimed in claim 4 , wherein the indium content x of the first quantum well layers is less than the indium content x of the at least one second quantum well layer. 7. The optoelectronic semiconductor chip as claimed in claim 1 , wherein the first barrier layers and the at least one second barrier layer each contain InxAlyGal-x-yP, InxAlyGal-x-yN or InxAlyGal-x-yAs, where 0≤x≤1, 0≤y≤1 and x+y≤1. 8. The optoelectronic semiconductor chip as claimed in claim 7 , wherein the aluminum content y of the first barrier layers is less than the aluminum content y of the at least one second barrier layer. 9. The optoelectronic semiconductor chip as claimed in claim 7 , wherein the indium content x of the first barrier layers is greater than the indium content x of the at least one second barrier layer. 10. The optoelectronic semiconductor chip as claimed in claim 1 , wherein the first region comprises at least twenty layer pairs composed of the first quantum well layers and the first barrier layers. 11. The optoelectronic semiconductor chip as claimed in claim 1 , wherein the second region comprises at least three layer pairs composed of the second quantum well layers and the second barrier layers. 12. The optoelectronic semiconductor chip as claimed in claim 1 , wherein the first region comprises at least five times as many layer pairs as the second region. 13. The optoelectronic semiconductor chip as claimed in claim 1 , wherein the first region comprises at least ten times as many layer pairs as the second region. 14. The optoelectronic semiconductor chip as claimed in claim 1 , wherein, for a temperature rise of Tl=25° C. to T2=85° C., a dominant wavelength of a radiation emitted by the active layer changes by less than ± 4 nm. 15. The optoelectronic semiconductor chip as claimed in claim 1 , wherein, for a temperature rise of Tl=25° C. to T2=85° C., a dominant wavelength of a radiation emitted by the active layer does not change.

Assignees

Inventors

Classifications

  • H01L33/06Primary

    Electricity · mapped topic

  • Electricity · mapped topic

  • having a plurality of light-emitting regions, e.g. multi-junction LEDs or light-emitting devices having photoluminescent regions within the bodies · CPC title

  • H10H20/812Primary

    within the light-emitting regions, e.g. having quantum confinement structures · CPC title

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What does patent US10217896B2 cover?
An optoelectronic semiconductor chip is disclosed. In an embodiment the optoelectronic semiconductor chip includes a p-type semiconductor region, an n-type semiconductor region, and an active layer arranged between the p-type semiconductor region and the n-type semiconductor region. The active layer is designed as a multiple quantum well structure, wherein the multiple quantum well structure ha…
Who is the assignee on this patent?
Osram Opto Semiconductors Gmbh
What technology area does this patent fall under?
Primary CPC classification H01L33/06. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Feb 26 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 3 related publications on this page (citations in our corpus or others sharing the same primary CPC).