Fabrication of a vertical fin field effect transistor with an asymmetric gate structure

Patent metadata

Field	Value
Publication number	US-10217863-B2
Application number	US-201615195498-A
Country	US
Kind code	B2
Filing date	Jun 28, 2016
Priority date	Jun 28, 2016
Publication date	Feb 26, 2019
Grant date	Feb 26, 2019

Abstract

A method of forming a vertical fin field effect transistor (vertical finFET) with two concentric gate structures, including forming one or more tubular vertical fins on a substrate, forming a first gate structure around an outer wall of at least one of the one or more tubular vertical fins, and forming a second gate structure within an inner wall of at least one of the one or more tubular vertical fins having the first gate structure around the outer wall.

First claim

What is claimed is:

1. A method of forming a vertical fin field effect transistor (vertical finFET) with two concentric gate structures, comprising:
forming one or more tubular vertical fins on a substrate;
forming a first bottom spacer on the substrate surrounding at least one of the one or more tubular vertical fins;
forming a first gate structure on the first bottom spacer and around an outer wall of the at least one of the one or more tubular vertical fins;
forming a second bottom spacer within the at least one of the one or more tubular vertical fins; and
forming a second gate structure on the second bottom spacer within an inner wall of the at least one of the one or more tubular vertical fins having the first gate structure around the outer wall.

2. The method of claim 1 , wherein the one or more tubular vertical fins are formed on the substrate by forming one sacrificial mandrel on the substrate for each of the one or more tubular vertical fins to be formed, and epitaxially growing the tubular vertical fin on the sacrificial mandrel, wherein the one or more tubular vertical fins are in direct contact with the substrate.

3. The method of claim 2 , wherein the sacrificial mandrel is silicon germanium.

4. The method of claim 2 , wherein the sacrificial mandrel is epitaxially grown on a single crystal silicon substrate.

5. The method of claim 1 , wherein the first gate structure includes a first gate dielectric layer formed on at least a portion of the first bottom spacer and outer wall of the at least one of the one or more tubular vertical fins, and a first gate fill layer formed on at least a portion of the first gate dielectric layer.

6. The method of claim 5 , wherein the second gate structure includes a second gate dielectric layer formed on at least a portion of the second bottom spacer and inner wall of the tubular vertical fin, and a second gate fill layer formed on at least a portion of the second gate dielectric layer.

7. The method of claim 6 , wherein the material of the first gate fill layer and the material of the second gate fill layer is tungsten (W), titanium (Ti), molybdenum (Mo), cobalt (Co), or a combination thereof.

8. The method of claim 7 , wherein the material of the first gate fill layer is different from the material of the second gate fill layer.

9. The method of claim 7 , wherein the first gate structure further includes a first work function layer between the first gate dielectric layer and first gate fill layer, and the second gate structure includes a second work function layer between the second gate dielectric layer and second gate fill layer.

10. The method of claim 9 , wherein the first work function layer and the second work function layer are different materials.

11. A method of forming a vertical fin field effect transistor (vertical finFET) with two concentric gate structures, comprising:
forming a plurality of sacrificial mandrels on a substrate;
reducing the lateral dimensions of the sacrificial mandrels;
forming a tubular vertical fin on each of the plurality of sacrificial mandrels;
forming a first gate structure around an outer wall of at least one of the plurality tubular vertical fins;
removing the plurality of sacrificial mandrels; and
forming a second gate structure on at least a portion of an inner wall of each tubular vertical fin.

12. The method of claim 11 , further comprising forming a doped region in the substrate above which each of the one or more vertical fins are formed.

13. The method of claim 11 , further comprising forming a first bottom spacer between the substrate surface and the first gate structure, and forming a second bottom spacer between the substrate surface and the second gate structure.

14. The method of claim 11 , wherein forming the tubular vertical fin on each of the plurality of sacrificial mandrels further includes forming additional substrate material on the surface of the substrate, so the distance from the top surface of the tubular vertical fin to the substrate surface is greater within the tubular vertical fin than the distance from the top surface of the tubular vertical fin to the substrate surface outside the tubular vertical fin.

15. A vertical fin field effect transistor (vertical finFET) with a concentric gate structure, comprising:
a tubular vertical fin directly on a substrate;
a first bottom spacer on the substrate adjacent to an outer wall of the tubular vertical fin;
a second bottom spacer on the substrate adjacent to an inner wall of the tubular vertical fin;
a first gate structure formed on at least a portion of the first bottom spacer and at least a portion of the outer wall of the tubular vertical fin; and
a second gate structure formed on at least a portion of the second bottom spacer and at least a portion of the inner wall of the tubular vertical fin.

16. The vertical finFET of claim 15 , wherein the first gate structure and the second gate structure are not electrically coupled together.

17. The vertical finFET of claim 15 , further comprising a doped region in the substrate below each of the one or more tubular vertical fins forming a bottom source drain, and a top source drain on at least a portion of the top surface of each of the one or more tubular vertical fins.

18. The vertical finFET of claim 15 , further comprising an interlayer dielectric on the first gate structure and the second gate structure, a first gate structure contact through the interlayer dielectric to the first gate structure, and a second gate structure contact through the interlayer dielectric to the second gate structure.

19. The vertical finFET of claim 15 , wherein the dimensions of the first gate structure and the second gate structure are asymmetric.

20. The vertical finFET of claim 15 , wherein the first gate structure includes a first gate dielectric layer, and the second gate structure includes a second gate dielectric layer, wherein the second gate dielectric layer is a different material than the first gate dielectric layer.

Assignees

• IBM

Inventors

• Mochizuki Shogo
• Wang Junli

Classifications

• H01L29/66484

  Electricity · mapped topic

• H01L29/4966

  Electricity · mapped topic

• H01L29/495

  Electricity · mapped topic

• H01L29/0847

  Electricity · mapped topic

• H01L29/66666

  Electricity · mapped topic