Semiconductor-on-insulator with back side heat dissipation

Patent metadata

Field	Value
Publication number	US-10217822-B2
Application number	US-201615241359-A
Country	US
Kind code	B2
Filing date	Aug 19, 2016
Priority date	Jul 15, 2009
Publication date	Feb 26, 2019
Grant date	Feb 26, 2019

Abstract

Embodiments of the present invention provide for the enhancement of transistors in a semiconductor structure using a strain layer. The structure comprises a patterned layer consisting of an excavated region and a pattern region, a strain layer located in the excavated region and on the pattern region, an active layer located above the strain layer, a field effect transistor formed in the active layer, and a handle layer located above the active layer. The field effect transistor comprises a source, a drain, and a channel. The channel lies completely within a lateral extent of the pattern region. The source and the drain each lie only partially within the lateral extent of the pattern region. The strain layer alters a carrier mobility of the channel. In some embodiments, the strain layer is introduced to the back side of a semiconductor-on-insulator structure.

First claim

What is claimed is:

1. A singulated semiconductor-on-insulator (SOI) structure comprising:
an active layer including a transistor having a source, a gate, and a drain;
a patterned layer formed on a back side of the active layer, wherein the patterned layer includes insulator material etched in a pattern, wherein the pattern includes a portion of insulator material formed below the gate, wherein a lateral dimension of the gate lies entirely within a lateral dimension of the portion of insulator material and the source and drain each lie only partially within the lateral dimension of the portion of insulator material; and
a strain layer deposited below the patterned layer and covering the portion of insulator material as well as an excavated region of the strain layer adjacent the portion of insulator material, wherein:
the excavated region extends laterally from below the source to beyond a periphery of the transistor;
wherein a lateral dimension of the excavated region is larger than a length of a channel of the transistor by at least a factor of ten.

2. The singulated SOI structure of claim 1 , wherein:
a ratio of a height of the patterned layer to a thickness of the strain layer is within a range of 0.75 to 1.5.

3. The singulated SOI structure of claim 2 , further comprising:
a buried insulator of the SOI structure that is in contact with both the patterned layer and the active layer; and
wherein the patterned layer is formed on the buried insulator.

4. The singulated SOI structure of claim 1 , further comprising:
a buried insulator of the SOI structure;
wherein the patterned layer includes the buried insulator.

5. The singulated SOI structure of claim 4 , further comprising:
a counter-strain layer formed on a back side of the strain layer.

6. A semiconductor-on-insulator (SOI) structure comprising:
a patterned layer formed in an insulating material of the SOI structure, the patterned layer having an excavated region and a pattern region;
a strain layer located beneath the patterned layer and in the excavated region and on the pattern region;
an active layer located above the strain layer and the patterned layer;
a transistor formed in the active layer, wherein the transistor includes a source, a drain, and a gate; and
a handle layer formed above the active layer;
wherein the gate lies completely within a lateral extent of the pattern region; and
wherein the source and the drain each lie only partially within the lateral extent of the pattern region, wherein:
the excavated region extends laterally from below the source to beyond a periphery of the transistor;
wherein a lateral dimension of the excavated region is larger than a length of a channel of the transistor by at least a factor of ten.

7. The SOI structure of claim 6 , wherein:
the patterned layer has a height equal to a depth of the excavated region;
the strain layer has a front surface in contact with the patterned layer and a back surface;
the strain layer has a thickness equal to a distance between the back surface and the front surface; and
a ratio of the height of the patterned layer to the thickness of the strain layer is within a range from 0.75 to 1.5.

8. The SOI structure of claim 7 , further comprising:
a buried insulator of the semiconductor-on-insulator structure that is in contact with both the patterned layer and the active layer; and
wherein the patterned layer is formed on the buried insulator.

9. The SOI structure of claim 6 , further comprising:
a buried insulator of the SOI structure;
wherein the patterned layer includes the buried insulator.

10. The SOI structure of claim 9 , further comprising:
a counter-strain layer formed on a back side of the strain layer.

11. A singulated semiconductor apparatus comprising:
an active layer including a plurality of dielectric layers and metal layers, the active layer further including a transistor;
a patterned layer of insulating material on a back side of the active layer, the patterned layer including a portion of remaining insulating material and an etched portion;
a strain layer formed on a back side of the patterned layer; and
a handle layer above a front side of the active layer;
wherein the transistor includes a gate, a source, and a drain;
wherein the portion of remaining insulating material is below the gate and extends at least from the source to the drain, and the source and the drain each lie only partially within a lateral extent of the remaining insulating material; and
wherein the strain layer is in contact with the active layer, and wherein the strain layer comprises silicon nitride.

12. The singulated semiconductor apparatus of claim 11 , wherein:
the etched portion has an etch depth;
the strain layer has a strain layer width; and
a ratio of the etch depth to the strain layer width is within a range from 0.75 to 1.5.

13. The singulated semiconductor apparatus of claim 11 , further comprising:
wherein a dimension of the etched portion measured along a direction parallel with a channel length of the transistor is larger than the channel length by at least a factor of ten.

14. The singulated semiconductor apparatus of claim 11 , further comprising:
a buried insulator layer in contact with the active layer and the strain layer.

15. The singulated semiconductor apparatus of claim 14 , wherein patterned layer includes the buried insulator layer.

16. The singulated semiconductor apparatus of claim 14 , wherein the buried insulator layer includes silicon dioxide.

17. The singulated semiconductor apparatus of claim 11 , wherein the handle layer comprises a semiconductor substrate bonded to the active layer.

Assignees

• Qualcomm Inc

Inventors

• Nygaard Paul A
• Molin Stuart B
• Stuber Michael A
• Aubain Max

Classifications

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W72/073

  of die-attach connectors · CPC title

• H10W72/50

  Bond wires · CPC title

• H10W72/07551

  characterised by changes in properties of the bond wires during the connecting · CPC title