Back-to-back stacked integrated circuit assembly and method of making

Patent metadata

Field	Value
Publication number	US-9390974-B2
Application number	US-201213725403-A
Country	US
Kind code	B2
Filing date	Dec 21, 2012
Priority date	Dec 21, 2012
Publication date	Jul 12, 2016
Grant date	Jul 12, 2016

Abstract

An integrated circuit assembly includes a first substrate and a second substrate, with active layers formed on the first surfaces of each substrate, and with the second surfaces of each substrate coupled together. A method of fabricating an integrated circuit assembly includes forming active layers on the first surfaces of each of two substrates, and coupling the second surfaces of the substrates together.

First claim

What is claimed is:

1. A method of forming an integrated circuit assembly, the method comprising:
providing a first substrate having a first surface and a second surface;
forming a first active layer on the first surface of the first substrate;
providing a second substrate having a first surf ace and a second surface, wherein the second substrate includes a second active layer formed on the first surface of the second substrate;
contact bonding the second surface of the second substrate to the second surface of the first substrate to form a bonded substrate assembly without a vertical electrical connection through the first substrate and the second substrate and without previously singulating the first substrate and the second substrate into individual chips; and
singulating the bonded substrate assembly into individual chips after contact bonding the second surface of the second substrate to the second surface of the first substrate.

2. The method of claim 1 wherein the step of providing a second substrate comprises:
providing a semiconductor-on-insulator including an insulating layer interposed between the second active layer and a handle layer, and removing at least a portion of the handle layer.

3. The method of claim 2 , wherein the handle layer is completely removed.

4. The method of claim 2 further comprising:
before the step of removing at least a portion of the handle layer, bonding a temporary carrier to the second active layer of the semiconductor-on-insulator; and
after the step of contact bonding the second surface of the second substrate to the second surface of the first substrate, removing the temporary carrier.

5. The method of claim 1 further comprising forming a metal bond pad on the first active layer.

6. The method of claim 1 further comprising forming a metal bond pad on the second active layer.

7. The method of claim 1 further comprising thinning the first substrate before contact bonding the second surface of the second substrate to the second surface of the first substrate.

8. The method of claim 1 wherein the first substrate is a semiconductor wafer.

9. The method of claim 8 , wherein the step of forming a first active layer on the first surface of the first substrate comprises forming a complementary metal-oxide-semiconductor circuit.

10. The method of claim 1 , wherein the first active layer or the second active layer includes passive devices.

11. The method of claim 1 , further comprising:
singulating the integrated circuit assembly into individual integrated circuit chips.

12. The method of claim 1 , further comprising:
electrically connecting a printed circuit board to the first active layer and the second active layer.

13. The method of claim 12 , wherein the step of electrically connecting a printed circuit board to the first active layer and the second active layer comprises:
forming a first metal bond pad on the first active layer;
forming a second metal bond pad on the second active layer;
forming a solder bump on the first metal bond pad on the first active layer;
attaching the solder bump to a third metal pad on the printed circuit board, and
wire bonding the second metal bond pad on the second active layer to a fourth metal pad on the printed circuit board.

14. The method of claim 1 , wherein the step of contact bonding the second surface of the second substrate to the second surface of the first substrate comprises:
applying an adhesive layer to the second surface of the first substrate; and contacting the second surface of the second substrate to the adhesive layer.

15. The method of claim 1 , wherein the step of contact bonding the second surface of the second substrate to the second surface of the first substrate comprises fusion bonding.

16. The method of claim 1 , wherein the step of contact bonding the second surface of the second substrate to the second surface of the first substrate comprises aligning the second substrate to the first substrate to an accuracy of 5 microns.

17. The method of claim 16 , further comprising:
electrically coupling a printed circuit board to the first active layer and the second active layer:
forming a first metal bond pad on the first active layer;
forming a second metal bond pad on the second active layer;
forming a solder bump on the first metal bond pad on the first active layer;
attaching the solder bump to a third metal pad on the printed circuit board, and
wire bonding the second metal bond pad on the second active layer to a fourth metal pad on the printed circuit board.

18. A method of forming an integrated circuit assembly, the method comprising:
contact bonding a first substrate to a second substrate, wherein the first substrate has a first side having a first active layer and a second side opposite the first side, further wherein the second substrate has a first side having a second active layer and a second side opposite the first side; wherein the contact bonding includes bonding the second side of the first substrate to the second side of the second substrate without use of a through silicon via (TSV) for electrical connection through the first substrate or second substrate; and
singulating the first and second substrates into at least one individual semiconductor chip after contact bonding the first substrate to the second substrate.

19. The method of claim 18 , further comprising:
forming a semiconductor-on-insulator including an insulating layer interposed between the second active layer and a handle layer, and removing at least a portion of the handle layer.

20. The method of claim 19 further comprising:
before the removing at least a portion of the handle layer, bonding a temporary carrier to the second active layer of the semiconductor-on-insulator; and
after the contact bonding, removing the temporary carrier.

21. The method of claim 18 , wherein the contact bonding includes at least one of:
applying an adhesive layer to the second surface of the first substrate and contacting the second surface of the second substrate to the adhesive layer; and
fusion bonding the second surface of the first substrate and the second surface of the second substrate.

Assignees

• Qualcomm Switch Corp
• Qualcomm Inc

Inventors

• Stuber Michael A
• Molin Stuart B

Classifications

• H10P72/7416

  used during dicing or grinding · CPC title

• H10P72/744

  Details of chemical or physical process used for separating the auxiliary support from a device or a wafer · CPC title

• H10P72/7402

  Wafer tapes, e.g. grinding or dicing support tapes · CPC title

• H10P72/74

  using temporarily an auxiliary support · CPC title

• H10P54/00

  Cutting or separating of wafers, substrates or parts of devices · CPC title