Method of forming resistors with controlled resistivity

Patent metadata

Field	Value
Publication number	US-10217809-B2
Application number	US-201715814029-A
Country	US
Kind code	B2
Filing date	Nov 15, 2017
Priority date	Jan 11, 2017
Publication date	Feb 26, 2019
Grant date	Feb 26, 2019

Abstract

The present application provides planar and stacked resistor structures that are embedded within an interconnect dielectric material in which the resistivity of an electrical conducting resistive material or electrical conducting resistive materials of the resistor structure can be tuned to a desired resistivity during the manufacturing of the resistor structure. Notably, a doped metallic insulator layer is formed atop a substrate. A controlled surface treatment process is then performed to an upper portion of the doped metallic insulator layer to convert the upper portion of the doped metallic insulator layer into an electrical conducting resistive material layer. The remaining doped metallic insulator layer and the electrical conducting resistive material layer are then patterned to provide the resistor structure.

First claim

What is claimed is:

1. A method of forming a semiconductor structure, the method comprising:
forming a doped metallic insulator layer having an insulating phase atop a substrate;
performing a controlled surface treatment process to an upper portion of the doped metallic insulator layer to convert the upper portion of the doped metallic insulator layer into an electrical conducting resistive material layer having an electrical conducting phase, the electrical conducting resistive material layer is selected from the group consisting of a metallic nitride, a metallic oxide, and a metallic nitride-oxide;
patterning the doped metallic insulator layer and the electrical conducting resistive material layer to provide a resistor structure comprising a remaining portion of the doped metallic insulator layer and a remaining portion of the electrical conducting resistive material layer; and
forming an interconnect dielectric material on the substrate and the resistor structure.

2. The method of claim 1 , wherein the controlled surface treatment process comprises a thermal process, a plasma process, a gas cluster ion beam process, an ion beam process or an ion implantation process.

3. The method of claim 1 , further comprising forming a first contact structure and a second contact structure in the interconnect dielectric material and contacting different portions of a topmost surface of resistor structure.

4. The method of claim 1 , wherein the controlled surface treatment process comprises a thermal process that is performed at a temperature from 50° C. to 600° C. and in an ambient containing at least one of nitrogen (N 2 ), oxygen (O 2 ), hydrogen (H 2 ), and argon (Ar).

5. The method of claim 1 , wherein the controlled surface treatment process comprises a plasma process that is performed at a temperature from 50° C. to 600° C. and in an ambient containing at least one of nitrogen (N 2 ), oxygen (O 2 ), hydrogen (H 2 ), and argon (Ar).

6. The method of claim 1 , wherein the controlled surface treatment process comprises an ion beam process in which an energy is from 10 eV to 100 eV is employed, and the ion beam contains at least one of nitrogen (N 2 ) ions, oxygen (O 2 ) ions, hydrogen (H 2 ) ions, and argon (Ar) ions.

7. The method of claim 1 , wherein the controlled surface treatment process comprises a gas cluster ion beam process in which an energy is from 10 eV to 30 eV is employed, and the gas cluster contains at least one of nitrogen (N 2 ) ions, oxygen (O 2 ) ions, hydrogen (H 2 ) ions, and argon (Ar) ions.

8. The method of claim 1 , wherein the controlled surface treatment process comprises an ion implantation process in which an energy is from 10 eV to 200 eV is employed, and the ion beam contains at least one of nitrogen (N 2 ) ions, oxygen (O 2 ) ions, hydrogen (H 2 ) ions, and argon (Ar) ions.

9. The method of claim 1 , wherein the doped metallic insulator is a nitrogen doped metal, an oxygen doped metal or a nitrogen and oxygen doped metal.

10. The method of claim 9 , wherein the metal is titanium (Ti), ruthenium (Ru), tungsten (W), platinum (Pt), cobalt (Co), rhodium (Rh) or manganese (Mn).

11. The method of claim 9 , wherein the metal is tantalum (Ta).

12. The method of claim 11 , wherein the electrical conducting resistive material is composed of tantalum nitride (TaN) and the doped metallic insulator is composed of Ta 3 N 5 .

13. A method of forming a semiconductor structure, the method comprising:
forming a first doped metallic insulator layer having an insulating phase atop a substrate;
performing a first controlled surface treatment process to the doped metallic insulator layer to convert an entirety of the first doped metallic insulator layer into a base electrical conducting resistive material layer having an electrical conducting phase,
forming a second doped metallic insulator layer having an insulating phase atop the base electrical conductive resistive material layer;
performing a second controlled surface treatment process to convert the upper portion of the second doped metallic insulator layer into an electrical conducting resistive material layer having an electrical conducting phase, the electrical conducting resistive material layer is selected from the group consisting of a metallic nitride, a metallic oxide, and a metallic nitride-oxide;
patterning the base electrical conducting resistive material layer, the doped metallic insulator layer and the electrical conducting resistive material layer to provide a resistor structure comprising a remaining portion of the base electrical conducting resistive material, a remaining portion of the doped metallic insulator layer and a remaining portion of the electrical conducting resistive material layer; and
forming an interconnect dielectric material on the substrate and the resistor structure.

14. The method of claim 13 , wherein the base electrical conducting resistive material layer is selected from the group consisting of a metallic nitride, a metallic oxide, and a metallic nitride-oxide.

15. The method of claim 14 , wherein the metallic nitride, a metallic oxide, or metallic nitride-oxide that provides the base electrical conducting resistive material comprises a metal that is the same as a metal present in the doped metallic insulator layer.

16. The method of claim 15 , wherein the metal is tantalum (Ta).

17. The method of claim 15 , wherein the metal is titanium (Ti), ruthenium (Ru), tungsten (W), platinum (Pt), cobalt (Co), rhodium (Rh) or manganese (Mn).

Assignees

• IBM

Inventors

• Edelstein Daniel C
• Yang Chih-Chao

Classifications

• H10P95/00

  Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass · CPC title

• H10P14/69393

  the material containing tantalum, e.g. Ta2O5 · CPC title

• H10P14/412

  Deposition of metallic or metal-silicide materials · CPC title

• H10W20/498

  Resistive arrangements or effects of, or between, wiring layers · CPC title

• H10W20/425

  Barrier, adhesion or liner layers · CPC title