Microstructure modulation for metal wafer-wafer bonding

Patent metadata

Field	Value
Publication number	US-10217725-B2
Application number	US-201715440807-A
Country	US
Kind code	B2
Filing date	Feb 23, 2017
Priority date	Feb 23, 2017
Publication date	Feb 26, 2019
Grant date	Feb 26, 2019

Abstract

A three-dimensional (3D) bonded semiconductor structure is provided in which a first bonding oxide layer of a first semiconductor structure is bonded to a second bonding oxide layer of a second semiconductor structure. Each of the first and second bonding oxide layers has a metallic bonding structure embedded therein, wherein each metallic bonding structure contains a columnar grain microstructure. Furthermore, at least one columnar grain extends across a bonding interface that is present between the metallic bonding structures. The presence of the columnar grain microstructure in the metallic bonding structures, together with at least one columnar grain microstructure extending across the bonding interface between the two bonded metallic bonding structures, can provide a 3D bonded structure having mechanical bonding strength and electrical performance enhancements.

First claim

What is claimed is:

1. A three-dimensional (3D) bonded semiconductor structure comprising:
a first structure comprising a first semiconductor wafer, a first interconnect structure, a first bonding oxide layer, and at least one first metallic bonding structure embedded in the first bonding oxide layer; and
a second semiconductor structure comprising a second semiconductor wafer, a second interconnect structure, a second bonding oxide layer, and at least one second metallic bonding structure embedded in the second bonding oxide layer, wherein each of the first and second metallic bonding structures has a columnar grain microstructure, and wherein a bonding interface is present between the first and second bonding oxide layers and another bonding interface is present between the at least one first and second metallic bonding structures, wherein at least one columnar grain extends across the another bonding interface that is present between the first and second metallic bonding structures.

2. The 3D bonded semiconductor structure of claim 1 , wherein each of the first and second interconnect structures comprises at least one interconnect dielectric material and one or more interconnect metallic structures embedded therein.

3. The 3D bonded semiconductor structure of claim 2 , wherein the at least one or more interconnect metallic structures are composed of copper, a copper-aluminum alloy, a copper manganese alloy, aluminum or an aluminum-copper alloy.

4. The 3D bonded semiconductor structure of claim 2 , wherein the one or more interconnect metallic structures include a same metal or metal alloy as the at least one first and second metallic bonding structures.

5. The 3D bonded semiconductor structure of claim 4 , wherein the same metal or metal alloy comprises copper.

6. The 3D bonded semiconductor structure of claim 1 , wherein each of the at least one first and second metallic bonding structures is composed of a metal or a metal alloy, wherein the metal or metal alloy is selected from copper, a copper-aluminum alloy, a copper manganese alloy, aluminum and an aluminum-copper alloy.

7. The 3D bonded semiconductor structure of claim 6 , wherein each of the at least one first and second metallic bonding structures is composed of copper.

8. The 3D bonded semiconductor structure of claim 1 , wherein each of the first and second bonding oxide layers is composed of silicon dioxide, tetraethylorthosilicate (TEOS), or fluorinated tetraethylorthosilicate (FTEOS).

9. The 3D bonded semiconductor structure of claim 1 , wherein the at least one first metallic bonding structure extends entirely through the first bonding oxide layer and contacts at least a portion of an interconnect metallic structure of the first interconnect structure, and the at least one second metallic bonding structure extends entirely through the second bonding oxide layer and contacts at least a portion of an interconnect metallic structure of the second interconnect structure.

10. The 3D bonded semiconductor structure of claim 1 , wherein each of the first and second semiconductor wafers comprises a semiconductor substrate containing one or more semiconductor devices thereon.

Assignees

• IBM

Inventors

• Yang Chih-Chao

Classifications

• H10W80/00

  Direct bonding of chips, wafers or substrates · CPC title

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P90/1914 Primary

  using bonding · CPC title

• H10P52/402

  of semiconductor materials · CPC title

• H10P10/12

  Bonding of semiconductor wafers or semiconductor substrates to semiconductor wafers or semiconductor substrates (preparing SOI wafers using bonding H10P90/1914) · CPC title