Semiconductor device package having an underfill barrier

Patent metadata

Field	Value
Publication number	US-10217649-B2
Application number	US-201715619415-A
Country	US
Kind code	B2
Filing date	Jun 9, 2017
Priority date	Jun 9, 2017
Publication date	Feb 26, 2019
Grant date	Feb 26, 2019

Abstract

A semiconductor device package includes a substrate, a semiconductor device, and an underfill. The substrate includes a top surface defining a mounting area, and a barrier section on the top surface and adjacent to the mounting area. The semiconductor device is mounted on the mounting area of the substrate. The underfill is disposed between the semiconductor device and the mounting area and the barrier section of the substrate. A contact angle between a surface of the underfill and the barrier section is greater than or equal to about 90 degrees.

First claim

What is claimed is:

1. A semiconductor device package, comprising;
a substrate including:
a top surface defining a mounting area, and
a barrier section on the top surface and adjacent to the mounting area;

a semiconductor device mounted on the mounting area of the substrate; and
an underfill disposed between the semiconductor device and the mounting area of the substrate, wherein a contact angle between a surface of the underfill and the barrier section is greater than or equal to about 90 degrees.

2. The semiconductor device package of claim 1 , wherein the barrier section is hydrophobic or super-hydrophobic.

3. The semiconductor device package of claim 1 , wherein the barrier section has a nano-scale or micro-scale roughness.

4. The semiconductor device package of claim 1 , wherein the barrier section includes a plurality of holes or protrusions.

5. The semiconductor device package of claim 1 , wherein the barrier section is continuously formed along at least three edges of the mounting area.

6. The semiconductor device package of claim 1 , wherein the top surface of the substrate is substantially coplanar with a surface of the barrier section.

7. The semiconductor device package of claim 1 , wherein the barrier section includes a coating comprising a polymer material and nano-particles dispersed in the polymer material.

8. The semiconductor device package of claim 1 , wherein the substrate further comprises a trapper section formed within the mounting area, wherein the trapper section is hydrophilic or super-hydrophilic.

9. The semiconductor device package of claim 8 , wherein the trapper section includes a hydrophilic coating or film.

10. The semiconductor device package of claim 8 , wherein the trapper section includes a film including a nano-scale porous structure.

11. The semiconductor device package of claim 8 , wherein the trapper section comprises a graphene oxide material.

12. The semiconductor device package of claim 11 , wherein the barrier section comprises a graphene material.

13. The semiconductor device package of claim 1 , wherein a width of the barrier section is greater than or equal to about 10 micrometers.

14. The semiconductor device package of claim 1 , wherein the underfill ends at an edge of the barrier section.

15. A substrate for a semiconductor device package, comprising:
a dielectric layer having a first surface;
a conductive pattern disposed in the dielectric layer; and
a barrier section in the dielectric layer and exposed from the first surface of the dielectric layer, wherein a surface of the barrier section is hydrophobic or super-hydrophobic.

16. The substrate of claim 15 , wherein the first surface defines a mounting area configured to mount a semiconductor device, and the barrier section is continuously formed along at least three edges of the mounting area.

17. The substrate of claim 15 , further comprising:
a trapper section in the dielectric layer, exposed from the first surface of the dielectric layer, and adjacent to the barrier section, wherein the trapper section is hydrophilic or super-hydrophilic.

18. The substrate of claim 15 , wherein a width of the barrier section is greater than or equal to about 10 micrometers.

19. The substrate of claim 15 , wherein the trapper section comprises a graphene oxide material.

20. The substrate of claim 19 , wherein the barrier section comprises a graphene material.

Assignees

• Advanced Semiconductor Eng

Inventors

• Lai Jin-Yuan
• Chen Tang-Yuan
• Lu Ying-Xu
• Chen Dao-Long
• Lin Kwang-Lung
• Hung Chih-Pin
• Chou Tse-Chuan
• Chen Ming-Hung
• Pan Chi-Hung

Classifications

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/07331

  Connecting techniques · CPC title

• H10W72/07321

  Aligning · CPC title

• H10W72/953

  not comprising solid metals or solid metalloids, e.g. polymers, ceramics or liquids · CPC title