Memory device including encoded data line-multiplexer

Patent metadata

Field	Value
Publication number	US-10217495-B2
Application number	US-201815863382-A
Country	US
Kind code	B2
Filing date	Jan 5, 2018
Priority date	Sep 21, 2015
Publication date	Feb 26, 2019
Grant date	Feb 26, 2019

Abstract

Some embodiments include apparatuses and methods having non-volatile memory cells, a data line associated with a group of non-volatile memory cells of the non-volatile memory cells, a first transistor coupled to the data line and a node, a second transistor coupled to the node and an additional node, a pull-up component coupled to the node and a supply node, and an additional pull-up component coupled to the additional node and the supply node.

First claim

What is claimed is:

1. An apparatus comprising:
first data lines associated with first memory cells;
second data lines associated with second memory cells;
a circuit to form a circuit path between a first node and a data line among the first data lines if a memory cell among the first memory cells is selected during an operation of retrieving information from at least one of the first memory cells, and to form a circuit path between a second node and a data line among the second data lines if a memory cell among the second memory cells is selected during an operation of retrieving information from at least one of the second memory cells; and
a selector to form a circuit path between an additional node and one of the first and second nodes and during the operation of retrieving information from at least one of the first and second memory cells, to decouple the first node from a supply node and to form a circuit path between the second node and the supply node if the memory cell among the first memory cells is selected, and to form a circuit path between the first node and the supply node and to decouple the second node from the supply node if the memory cell among the second memory cells is selected.

2. The apparatus of claim 1 , further comprising a component to charge the additional node before the selector forms the circuit path between the additional node and one of the first and second nodes.

3. The apparatus of claim 1 , further comprising an output circuit to control at least one transistor coupled in series between the additional node and the supply node based on voltages at the first and second nodes.

4. The apparatus of claim 1 , further comprising an output circuit to generate output information based on a voltage at the additional node, the output information having a value indicating a value of information stored in one of the first and second memory cells.

5. The apparatus of claim 1 , wherein the circuit includes:
a first transistor coupled between the first node and one of the first data lines; and
a second transistor coupled between the first node and another one of the first data lines.

6. The apparatus of claim 5 , wherein the circuit includes:
a third transistor coupled between the second node and one of the second data lines; and
a fourth transistor coupled between the second node and another one of the second data lines.

7. The apparatus of claim 1 , wherein the selector includes:
a first transistor coupled between the first node and the additional node; and
a second transistor coupled between the second node and the additional node.

8. The apparatus of claim 7 , wherein the selector includes:
a first pull-up component coupled to the first node and the supply node; and
a second pull-up component coupled to the second node and the supply node.

9. The apparatus of claim 8 , wherein the selector further includes:
a first logic gate having an output coupled to the first pull-up component; and
a second logic gate having an output coupled to the second pull-up component.

10. The apparatus of claim 1 , further comprising an output stage, the output stage including transistors coupled in series between the additional node and the supply node.

11. The apparatus of claim 10 , wherein the output stage includes a logic gate having an output coupled to a gate of one of the transistors coupled in series.

12. The apparatus of claim 11 , wherein the output stage includes a pull-up component coupled to the additional node and the supply node.

13. An apparatus comprising:
first data lines associate with first memory cells;
second data lines associated with second memory cells;
a circuit to form a circuit path between a first node and a data line among the first data lines based on a first combination of signals from a decoder and to form a circuit path between a second node and a data line among the second data lines based on a second combination of the signals from the decoder; and
a selector to form a circuit path between an additional node and one of the first and second nodes based on one of the first and second combinations of the signals from the decoder, to decouple the first node from a supply node and to form a circuit path between the second node and the supply node based on the first combination of the signals from the decoder, and to form a circuit path between the first node and the supply node and to decouple the second node from the supply node based on the second combination of the signals from the decoder.

14. The apparatus of claim 13 , wherein the circuit includes:
a first transistor coupled between the first node and one of the first data lines;
a second transistor coupled between the first node and another one of the first data lines;
a third transistor coupled between the second node and one of the second data lines; and
a fourth transistor coupled between the second node and another one of the second data lines.

15. The apparatus of claim 13 , wherein the selector includes:
a first transistor coupled between the first node and the additional node; and
a second transistor coupled between the second node and the additional node.

16. The apparatus of claim 15 , wherein the selector includes:
a first pull-up component coupled to the first node and the supply node; and
a second pull-up component coupled to the second node and the supply node.

17. The apparatus of claim 16 , wherein the selector further includes:
a first logic gate having an output coupled to the first pull-up component; and
a second logic gate having an output coupled to the second pull-up component.

18. An apparatus comprising:
a processing core included in a die; and
a read-only-memory (ROM) device included in the die and coupled to the processing core, the ROM including:
first data lines associated first memory cells;
second data lines associated with second memory cells;
a circuit to form a circuit path between a first node and a data line among the first data lines if a memory cell among the first memory cells is selected during an operation of retrieving information from at least one of the first memory cells, and to form a circuit path between a second node and a data line among the second data lines if a memory cell among the second memory cells is selected during an operation of retrieving information from at least one of the second memory cells; and
a selector to form a circuit path between an additional node and one of the first and second nodes and during the operation of retrieving information from at least one of the first and second memory cells, to decouple the first node from a supply node and to form a circuit path between the second node and the supply node if the memory cell among the first memory cells is selected, and to form a circuit path between the first node and the supply node and to decouple the second node from the supply node if the memory cell among the second memory cells is selected.

19. The apparatus of claim 18 , wherein the processing core includes a node coupled to the supply node.

20. The apparatus of claim 18 , wherein the processing core is part of a central processing unit.

21. The apparatus of claim 1 , wherein the selector is to form a circuit path between the additional node and the first node if the memory cell among the first memory cells is selected, and to form a circuit path between the additional node and the second node if the memory cell among the second memory cells is selected.

Assignees

• Intel Corp

Inventors

• Kulkarni Jaydeep

Classifications

• G11C2207/005

  Transfer gates, i.e. gates coupling the sense amplifier output to data lines, I/O lines or global bit lines · CPC title

• G11C7/1048

  Data bus control circuits, e.g. precharging, presetting, equalising · CPC title

• G11C8/08

  Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines · CPC title

• G11C7/12 Primary

  Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines · CPC title

• G11C8/10

  Decoders · CPC title