Memory device including encoded data line-multiplexer

Patent metadata

Field	Value
Publication number	US-9905278-B2
Application number	US-201514859884-A
Country	US
Kind code	B2
Filing date	Sep 21, 2015
Priority date	Sep 21, 2015
Publication date	Feb 27, 2018
Grant date	Feb 27, 2018

Abstract

Some embodiments include apparatuses and methods having non-volatile memory cells, a data line associated with a group of non-volatile memory cells of the non-volatile memory cells, a first transistor coupled to the data line and a node, a second transistor coupled to the node and an additional node, a pull-up component coupled to the node and a supply node, and an additional pull-up component coupled to the additional node and the supply node.

First claim

What is claimed is:

1. An apparatus comprising:
non-volatile memory cells;
a data line associated with a group of non-volatile memory cells of the non-volatile memory cells;
a first transistor coupled to the data line and a node;
a second transistor coupled to the node and an additional node;
a pull-up component coupled to the node and a supply node, the pull-up component including a transistor having a gate terminal coupled to a gate terminal of the second transistor; and
an additional pull-up component coupled to the additional node and the supply node.

2. The apparatus of claim 1 , further comprising:
an additional data line associated with an additional group of non-volatile memory cells of the non-volatile memory cells;
a third transistor, wherein the node is a first node and the third transistor is coupled to the additional data line and a second node;
a fourth transistor coupled to the second node and the additional node, wherein the pull-up component is a first pull-up component; and
a second pull-up component coupled to the second node and the supply node.

3. The apparatus of claim 2 , further comprising a decoder having a first output coupled to a gate terminal of the first transistor and to a second output coupled to a gate terminal of the third transistor.

4. An apparatus comprising:
non-volatile memory cells;
a data line associated with a group of non-volatile memory cells of the non-volatile memory cells;
a first transistor coupled to the data line and a node;
a second transistor coupled to the node and an additional node;
a pull-up component coupled to the node and a supply node;
an additional pull-up component coupled to the additional node and the supply node;
at least one transistor coupled between the additional node and the supply node; and
a logic gate having an input coupled to the node and an output coupled to a gate terminal of the at least one transistor.

5. An apparatus comprising:
non-volatile memory cells;
a data line associated with a group of non-volatile memory cells of the non-volatile memory cells;
a first transistor coupled to the data line and a node;
a second transistor coupled to the node and an additional node;
a pull-up component coupled to the node and a supply node;
an additional pull-up component coupled to the additional node and the supply node;
an additional data line associated with an additional group of non-volatile memory cells of the non-volatile memory cells;
a third transistor, wherein the node is a first node and the third transistor is coupled to the additional data line and a second node;
a fourth transistor coupled to the second node and the additional node, wherein the pull-up component is a first pull-up component;
a second pull-up component coupled to the second node and the supply node;
a decoder having a first output coupled to a gate terminal of the first transistor and to a second output coupled to a gate terminal of the third transistor; and
a logic gate having an input coupled to the gate terminal of the first transistor, and an output coupled to a gate terminal of the second transistor and to a gate terminal of a transistor included in the first pull-up component.

6. The apparatus of claim 5 , further comprising an additional logic gate having an input coupled to a gate terminal of the third transistor, and an output coupled to a gate terminal of the fourth transistor and a gate terminal of a transistor included in the second pull-up component.

7. An apparatus comprising:
first data lines associated first memory cells;
second data lines associated with second memory cells;
a circuit including first transistors and second transistors, each of the first data lines coupled to a first node through one of the first transistors, each of the second data lines coupled to a second node through one of the second transistors;
a selector including a first transistor coupled to the first node and an additional node, a second transistor coupled to the second node and the additional node, a first pull-up component coupled to the first node and a supply node, the first pull-up component including a transistor having a gate terminal coupled to a gate terminal of the first transistor, and a second pull-up component coupled to the second node and the supply node, the second pull-up component including a transistor having a gate terminal coupled to a gate terminal of the second transistor; and
an additional pull-up component coupled to the additional node and the supply node.

8. The apparatus of claim 7 , wherein each of the first and second transistors includes a gate coupled to an output of a decoder.

9. The apparatus of claim 7 , wherein the first pull-up component includes only one transistor coupled between the first node and the supply node, and the second pull-up component includes only one transistor coupled between the second node and the supply node.

10. The apparatus of claim 7 , wherein the additional the pull-up component includes a transistor coupled between the additional node and the supply node.

11. The apparatus of claim 7 , wherein the first and second memory cells include read-only memory cells.

12. An apparatus comprising:
first data lines associated first memory cells;
second data lines associated with second memory cells;
a circuit including first transistors and second transistors, each of the first data lines coupled to a first node through one of the first transistors, each of the second data lines coupled to a second node through one of the second transistors;
a selector including a first transistor coupled to the first node and an additional node, a second transistor coupled to the second node and the additional node, a first pull-up component coupled to the first node and a supply node, and a second pull-up component coupled to the second node and the supply node;
an additional pull-up component coupled to the additional node and the supply node;
a plurality of transistors coupled in series between the additional node and the supply node; and
a logic gate having a first input coupled to the first node, a second input coupled to the second node, and an output coupled to a gate terminal of at least one transistor in the plurality of transistors.

13. An apparatus comprising:
first data lines associated first memory cells;
second data lines associated with second memory cells;
a circuit including first transistors and second transistors, each of the first data lines coupled to a first node through one of the first transistors, each of the second data lines coupled to a second node through one of the second transistors;
a selector including a first transistor coupled to the first node and an additional node, a second transistor coupled to the second node and the additional node, a first pull-up component coupled to the first node and a supply node, and a second pull-up component coupled to the second node and the supply node; and
an additional pull-up component coupled to the additional node and the supply node wherein the selector further includes:
a first logic gate having inputs coupled to gate terminals of the first transistors of the circuit, and an output coupled to the first transistor of the selector and the first pull-up component; and
a second logic gate having inputs coupled to gate terminals of the second transistors of the circuit, and an output coupled to the second transistor of the selector and the second pull-up component.

14. An apparatus comprising:
a processing core included in a die; and
a read-only-memory (ROM) device included in the die and coupled to the processing core, th

Assignees

• Intel Corp

Inventors

• Kulkarni Jaydeep

Classifications

• G11C2207/005

  Transfer gates, i.e. gates coupling the sense amplifier output to data lines, I/O lines or global bit lines · CPC title

• G11C17/12

  using field-effect devices · CPC title

• G11C7/1048

  Data bus control circuits, e.g. precharging, presetting, equalising · CPC title

• G11C7/12 Primary

  Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines · CPC title

• G11C8/10

  Decoders · CPC title