High performance interconnect physical layer

Patent metadata

Field	Value
Publication number	US-9612986-B2
Application number	US-201414538871-A
Country	US
Kind code	B2
Filing date	Nov 12, 2014
Priority date	Oct 22, 2012
Publication date	Apr 4, 2017
Grant date	Apr 4, 2017

Abstract

A set of training sequences is generated, each training sequence to include a respective training sequence header, and the training sequence header is to be DC-balanced over the set of training sequences. The set of training sequences can be combined with electric ordered sets to form supersequences for use in such tasks as link adaptation, link state transitions, byte lock, deskew, and other tasks.

First claim

What is claimed is:

1. An apparatus comprising:
protocol layer logic, link layer logic, and physical layer logic;
the physical layer logic comprising a drift buffer, a transmitter, and a receiver, wherein the physical layer logic is to support differential signaling, wherein the drift buffer is to transfer received bit streams to a local clock domain;
the physical layer logic to enter a polling state from another state defined in a state machine, wherein the polling state is one of a plurality of states defined in the state machine for initialization of a link, and the physical layer logic, when in the polling state, is to
adapt the receiver,
initialize the drift buffer,
identify a symbol boundary,
lock on a training sequence sent during the polling state based on a header of the training sequence to identify boundaries between a series of training sequences sent in a pattern corresponding to the polling state,
initiate deskew of the plurality of lanes, and
exit the polling state in response to an acknowledgement.

2. The apparatus of claim 1 , wherein in response to the physical layer logic to exit the polling state, the physical layer logic is to initiate an in-band reset using an electrical idle ordered set (EIOS).

3. The apparatus of claim 1 , wherein the physical layer logic to lock on a training sequence comprises the physical layer logic to lock to an electrical idle ordered set (EIOS) and a training sequence header.

4. The apparatus of claim 1 , further comprising a remote device coupled to the plurality of lanes, wherein a skew between the plurality of lanes is not to exceed a maximum number of unit intervals (UI) at an operational speed.

5. The apparatus of claim 1 , wherein receiver is capable to perform latency fixing.

6. The apparatus of claim 1 , wherein the protocol logic is to support cache coherent transactions and non-coherent transactions.

7. The apparatus of claim 1 , wherein the physical layer logic, link layer logic, and protocol layer logic are included in a processor coupled in a first socket of a server with at least two sockets.

8. The apparatus of claim 1 , wherein the physical layer logic, link layer logic, and protocol layer logic are included in a system on a chip (SoC).

9. The apparatus of claim 8 , wherein the SoC is coupled to a plurality of other SoCs in a micro-server.

10. The apparatus of claim 8 , further comprising a transceiver for wireless communication.

11. The apparatus of claim 1 , wherein the physical layer logic is to exit the polling state to one of a loopback state or a link width state in response to the acknowledgement.

12. The apparatus of claim 11 , wherein the link comprises a plurality of lanes, loopback is to be performed on at least a subset of the lanes in the loopback state, and a lane map is to be defined for the link in the link width state.

13. An apparatus comprising
a controller to interface between at least a first processor to recognize a first instruction set and second processor to recognize a second instruction set that is different from the first instruction set, the controller comprising protocol layer logic, link layer logic, and physical layer logic, the protocol layer to support cache coherent transactions and the physical layer logic comprising a drift buffer, a transmitter, and a receiver,
wherein the physical layer logic is to couple to a plurality of lanes of a differential interconnect, the physical layer logic is to enter a polling state, wherein the polling state is one of a plurality of states defined in a state machine for initialization of a link and the physical logic, when in the polling state, is to adapt the receiver, initialize the drift buffer, identify a symbol boundary, lock on a training sequence sent during the polling state based on a header of the training sequence to identify boundaries between a series of training sequences sent in a pattern corresponding to the polling state, initiate deskew of the plurality of lanes, and exit the polling state in response to an acknowledgement.

14. The apparatus of claim 13 , wherein in response to the physical layer logic to exit the polling state, the physical layer logic is to initiate an in-band reset using an electrical idle ordered set (EIOS).

15. The apparatus of claim 13 , wherein the physical layer logic to lock on a training sequence comprises the physical layer logic to lock to an electrical idle ordered set (EIOS) and a training sequence header.

16. The apparatus of claim 13 , wherein the first and the second processor are coupled to the controller.

17. The apparatus of claim 16 , wherein the first instruction set comprises an Intel® based instruction set.

18. A computer readable medium including code, when executed, to cause logic of a layered protocol stack of a device, when in a polling state, to:
adapt a receiver of the layered protocol stack,
initialize a drift buffer of the layered protocol stack, wherein the drift buffer is to transfer received bit streams to a local clock domain,
identify a symbol boundary,
lock on a training sequence sent during the polling state based on a header of the training sequence, wherein the training sequence is one of a series of training sequences sent in a pattern defined for the polling state, the pattern comprises a repeating pattern of an electrical ordered set (EOS) followed by a defined number of training sequences, and locking on the training sequence identifies boundaries between the series of training sequences,
initiate deskew of the plurality of lanes, and
exit the polling state in response to an acknowledgement, wherein the polling state is one of a plurality of states defined in a state machine for initialization of a link, and the plurality of states further comprise a reset state, a receiver detect state, a transmitter detect state, and a configuration state.

19. The computer readable medium of claim 18 , wherein the code, when executed is further to cause logic, after an exit from the polling state, to initiate an in-band reset using an electrical idle ordered set (EIOS).

20. The computer readable medium of claim 18 , wherein the repeating pattern comprises an electrical idle exit ordered set (EIEOS) followed by a series of thirty training sequences.

Assignees

• Intel Corp

Inventors

• Iyer Venkatraman
• Jue Darren S
• Iyer Sitaraman

Classifications

• G06F13/4004 Primary

  Coupling between buses · CPC title

• G06F13/4221

  being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus · CPC title

• G06N20/00

  Machine learning · CPC title

• G06N99/005

  Physics · mapped topic

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title