Adaptive error correction codes for data storage systems

Patent metadata

Field	Value
Publication number	US-10216574-B2
Application number	US-201414570820-A
Country	US
Kind code	B2
Filing date	Dec 15, 2014
Priority date	Oct 24, 2012
Publication date	Feb 26, 2019
Grant date	Feb 26, 2019

Abstract

A data storage system configured to adaptively code data is disclosed. In one embodiment, a data storage system controller determines a common memory page size, such as an E-page size, for a non-volatile memory array. Based on the common memory page size, the controller selects a low-density parity-check (LDPC) code word length from a plurality of pre-defined LDPC code word lengths. The controller determines LDPC coding parameters for coding data written to or read from the memory array based on the selected LDPC code word length. By using the plurality of pre-defined LDPC code word lengths, the data storage system can support multiple non-volatile memory page formats, including memory page formats in which the common memory page size does not equal any LDPC code word length of the plurality of pre-defined LDPC code word lengths. Flexibility and efficiency of data coding can thereby be achieved.

First claim

What is claimed is:

1. A data storage system, comprising:
a non-volatile memory array comprising a plurality of memory pages; and
a controller configured to:
access coding parameters used to encode user data and parity data to be stored in the plurality of memory pages;
encode, using the coding parameters, first user data and first parity data as a first data unit;
store the first data unit in the plurality of memory pages;
decode, using the coding parameters, the first data unit retrieved from the plurality of memory pages;
detect a first number of bit errors encountered during decoding the first data unit retrieved from the plurality of memory pages;
in response to determining that the first number of bit errors exceeds a first threshold, adjust the coding parameters to increase an amount of parity data per total data that is included in data units subsequently encoded and stored in the plurality of memory pages; and
encode, using the adjusted coding parameters, second user data and second parity data as a second data unit to be stored in the plurality of memory pages.

2. The data storage system of claim 1 , wherein the controller is further configured to:
store the second data unit in the plurality of memory pages;
decode, using the adjusted coding parameters, the second data unit retrieved from the plurality of memory pages;
detect a second number of bit errors encountered during decoding the second data unit retrieved from the plurality of memory pages;
in response to determining that the second number of bit errors exceeds a second threshold greater than the first threshold, modify the adjusted coding parameters to increase the amount of parity per total data that is included in the data units subsequently encoded and stored in the plurality of memory pages; and
encode, using the modified coding parameters, third user data and third parity data as a third data unit to be stored in the plurality of memory pages.

3. The data storage system of claim 1 , wherein the coding parameters comprise low-density parity-check (LDPC) coding parameters including a P matrix size and a column weight, and the controller is configured to adjust the coding parameters by changing at least one of the P matrix size and the column weight.

4. The data storage system of claim 1 , wherein the controller is configured to access alternative coding parameters used to encode the user data and the parity data to be stored in a portion of the non-volatile memory array other than the plurality of memory pages, the alternative coding parameters being different from the coding parameters.

5. The data storage system of claim 1 , wherein the controller is configured to adjust the coding parameters in response to determining that the first number of bit errors exceeds the first threshold and that a limit on the amount of parity per total data that is included in the data units has not been reached.

6. In a data storage system comprising a controller, a method of coding data, the method comprising:
accessing coding parameters used to encode user data and parity data to be stored in a plurality of memory pages of a non-volatile memory array;
encoding, using the coding parameters, first user data and first parity data as a first data unit;
storing the first data unit in the plurality of memory pages;
decoding, using the coding parameters, the first data unit retrieved from the plurality of memory pages;
detecting a first number of bit errors encountered during decoding the first data unit retrieved from the plurality of memory pages;
in response to determining that the first number of bit errors exceeds a first threshold, adjusting the coding parameters to increase an amount of parity data per total data that is included in data units subsequently encoded and stored in the plurality of memory pages; and
encoding, using the adjusted coding parameters, second user data and second parity data as a second data unit to be stored in the plurality of memory pages.

7. The method of claim 6 , further comprising:
storing the second data unit in the plurality of memory pages;
decoding, using the adjusted coding parameters, the second data unit retrieved from the plurality of memory pages;
detecting a second number of bit errors encountered during decoding the second data unit retrieved from the plurality of memory pages;
in response to determining that the second number of bit errors exceeds a second threshold greater than the first threshold, modifying the adjusted coding parameters to increase the amount of parity per total data that is included in the data units subsequently encoded and stored in the plurality of memory pages; and
encoding, using the modified coding parameters, third user data and third parity data as a third data unit to be stored in the plurality of memory pages.

8. The method of claim 6 , wherein the coding parameters comprise low-density parity-check (LDPC) coding parameters including a P matrix size and a column weight, and wherein said adjusting the coding parameters comprises changing at least one of the P matrix size and the column weight.

Assignees

• Western Digital Tech Inc

Inventors

• Lu Guangming

Classifications

• H03M13/35

  Unequal or adaptive error protection, e.g. by providing a different level of protection according to significance of source information or by adapting the coding according to the change of transmission channel characteristics · CPC title

• G06F11/1048

  using arrangements adapted for a specific error detection or correction feature · CPC title

• H03M13/6516

  Support of multiple code parameters, e.g. generalized Reed-Solomon decoder for a variety of generator polynomials or Galois fields · CPC title

• G06F11/1072 Primary

  in multilevel memories · CPC title

• H03M13/353

  Adaptation to the channel · CPC title