Virtual image processor instruction set architecture (ISA) and memory model and exemplary target hardware having a two-dimensional shift array structure

Patent metadata

Field	Value
Publication number	US-10216487-B2
Application number	US-201715591984-A
Country	US
Kind code	B2
Filing date	May 10, 2017
Priority date	Apr 23, 2015
Publication date	Feb 26, 2019
Grant date	Feb 26, 2019

Abstract

A method is described that includes instantiating, within an application software development environment, a virtual processor having an instruction set architecture and memory model that contemplate first and second regions of reserved memory. The first reserved region is to keep data of an input image array. The second reserved region is to keep data of an output image array. The method also includes simulating execution of a memory load instruction of the instruction set architecture by automatically targeting the first reserved region and identifying desired input data with first and second coordinates relative to the virtual processor's position within an orthogonal coordinate system and expressed in the instruction format of the memory load instruction.

First claim

The invention claimed is:

1. A computer implemented method comprising:
providing a simulation environment for simulating operations of a virtual representation of processing hardware, wherein the virtual representation of processing hardware comprises a plurality of virtual processors and a memory model in which each virtual processor is associated with a respective line group position in a two-dimensional region of image data, each respective line group position in the two-dimensional region of image data having a respective x-coordinate and a respective y-coordinate;
receiving, in the simulation environment, an instruction having two-dimensional relative addressing, wherein the instruction comprises a two-dimensional relative address comprising an x-offset and a y-offset, wherein the two-dimensional relative address represents a location in the two-dimensional region of image data relative to the line group position associated with the virtual processor that executes the instruction; and
executing the instruction on each virtual processor of the plurality of virtual processors of the virtual representation of processing hardware, thereby simulating operations of an image processor having a two-dimensional shift register array and a two-dimensional array of processing elements, the executing including:
determining a first x-coordinate and a first y-coordinate of the line group position associated with the virtual processor,
computing a second x-coordinate by applying the x-offset of the instruction to the first x-coordinate of the line group position,
computing a second y-coordinate by applying the y-offset of the instruction to the first y-coordinate of the line group position, and
computing a result of executing the instruction using data stored at a second location in the two-dimensional region of image data, the second location being identified by the second x-coordinate and the second y-coordinate.

2. The method of claim 1 , wherein the instruction is a load instruction, and wherein computing a result of executing the instruction using data stored at the second location in the two-dimensional region of image data identified by the second x-coordinate and the second y-coordinate comprises:
obtaining data stored at the second location in the two-dimensional region of image data; and
copying the data into one or more registers of the virtual processor.

3. The method of claim 1 , wherein the instruction is a store instruction, and wherein computing a result of executing the instruction using data stored at the second location in the two-dimensional region of image data identified by the second x-coordinate and the second y-coordinate comprises:
obtaining data stored in one or more registers of the virtual processor; and
writing the data to the second location in the two-dimensional region of image data.

4. The method of claim 1 , wherein the memory model of the virtual representation of processing hardware comprises a respective private scratchpad region dedicated to each virtual processor, wherein for each virtual scratchpad region dedicated to a particular virtual processor, every other virtual processor cannot read from or write to the virtual scratchpad region dedicated to the particular virtual processor.

5. The method of claim 1 , wherein the two-dimensional region of image data is an output region of image data, and wherein the memory model of the virtual representation comprises a separate input region of image data,
wherein load instructions of the simulation environment cause the virtual processor to read from the input region of image data, and
wherein store instructions of the simulation environment cause the virtual processor to write to the output region of image data.

6. The method of claim 1 , wherein the memory model of the virtual representation of processing hardware comprises a constant look-up table, and further comprising:
receiving a second instruction that loads a value from the constant look-up table; and
simulating execution of the second instruction, including obtaining the value from the constant look-up table and broadcasting the obtained value from the constant look-up table to registers of each of the plurality of virtual processors.

7. The method of claim 1 , further comprising instantiating, within the simulation environment, one virtual processor for each location within the two-dimensional region of image data.

8. A system comprising:
one or more computers and one or more storage devices storing instructions that are operable, when executed by the one or more computers, to cause the one or more computers to perform operations comprising:
providing a simulation environment for simulating operations of a virtual representation of processing hardware, wherein the virtual representation of processing hardware comprises a plurality of virtual processors and a memory model in which each virtual processor is associated with a respective line group position in a two-dimensional region of image data, each respective line group position in the two-dimensional region of image data having a respective x-coordinate and a respective y-coordinate;
receiving, in the simulation environment, an instruction having two-dimensional relative addressing, wherein the instruction comprises a two-dimensional relative address comprising an x-offset and a y-offset, wherein the two-dimensional relative address represents a location in the two-dimensional region of image data relative to the line group position associated with the virtual processor that executes the instruction; and
executing the instruction on each virtual processor of the plurality of virtual processors of the virtual representation of processing hardware, thereby simulating operations of an image processor having a two-dimensional shift register array and a two-dimensional array of processing elements, the executing including:
determining a first x-coordinate and a first y-coordinate of the line group position associated with the virtual processor,
computing a second x-coordinate by applying the x-offset of the instruction to the first x-coordinate of the line group position,
computing a second y-coordinate by applying the y-offset of the instruction to the first y-coordinate of the line group position, and
computing a result of executing the instruction using data stored at a second location in the two-dimensional region of image data, the second location being identified by the second x-coordinate and the second y-coordinate.

9. The system of claim 8 , wherein the instruction is a load instruction, and wherein computing a result of executing the instruction using data stored at the second location in the two-dimensional region of image data identified by the second x-coordinate and the second y-coordinate comprises:
obtaining data stored at the second location in the two-dimensional region of image data; and
copying the data into one or more registers of the virtual processor.

10. The system of claim 8 , wherein the instruction is a store instruction, and wherein computing a result of executing the instruction using data stored at the second location in the two-dimensional region of image data identified by the second x-coordinate and the second y-coordinate comprises:
obtaining data stored in one or more registers of the virtual processor; and
writing the data to the second location in the two-dimensional region of image data.

11. The system of claim 8 , wherein the memory model of the virtual representation of processing hardware comprises a respective private scratchpad region dedicated to each virtual processor, wherein for each virtual scratchpad region dedicated to a particular virt

Assignees

• Google Llc

Inventors

• Meixner Albert
• Shacham Ofer
• Patterson David
• Finchelstein Daniel Frederic
• Zhu Qiuling
• Redgrave Jason Rupert

Classifications

• G06T1/20 Primary

  Processor architectures; Processor configuration, e.g. pipelining · CPC title

• G06F9/30

  Arrangements for executing machine instructions, e.g. instruction decode (for executing microinstructions G06F9/22) · CPC title

• G06F9/3004

  to perform operations on memory · CPC title

• G06F8/20 Primary

  Software design · CPC title

• G06F30/20

  Design optimisation, verification or simulation (optimisation, verification or simulation of circuit designs G06F30/30) · CPC title