Method and structure providing optical isolation of a waveguide on a silicon-on-insulator substrate

Patent metadata

Field	Value
Publication number	US-10215921-B2
Application number	US-201715648326-A
Country	US
Kind code	B2
Filing date	Jul 12, 2017
Priority date	Jun 4, 2012
Publication date	Feb 26, 2019
Grant date	Feb 26, 2019

Abstract

Disclosed are a method and structure providing a silicon-on-insulator substrate on which photonic devices are formed and in which a core material of a waveguide is optically decoupled from a support substrate by a shallow trench isolation region.

First claim

What is claimed as new and desired to be protected by Letters Patent of the United States is:

1. An integrated structure comprising:
a first semiconductor substrate having a shallow trench isolation region formed therein, the trench of the isolation region being filled with a dielectric material having a first index of refraction, wherein the dielectric material comprises silicon dioxide; and
a second substrate attached to the first substrate and including a dielectric material facing the first substrate and a waveguide formed of a semiconductor material over the dielectric material, the waveguide being formed of a material having a second index of refraction greater than the first index of refraction and being located over the shallow trench isolation region.

2. A structure as in claim 1 , wherein the combined thickness of the dielectric material facing the second substrate and the shallow trench isolation region is at least 1000 nm.

3. A structure as in claim 1 , wherein the first and second substrates comprise silicon.

4. A structure as in claim 1 , wherein the waveguide comprises a core region surrounded by a cladding region, the cladding region being formed at least in part by the dielectric material on the second substrate.

5. A structure as in claim 1 , wherein the core region comprises silicon and the cladding region comprises silicon dioxide.

6. A structure as in claim 1 , further comprising an area of the semiconductor material of the second substrate on which an electronic circuit element is formed.

7. A structure as in claim 1 , wherein the attached first and second substrates form a silicon-on-insulator structure.

8. A structure as in claim 1 , further comprising a dielectric material over the semiconductor material of the second substrate.

9. A structure as in claim 8 , wherein the dielectric material over the semiconductor material of the second substrate is part of an interlayer dielectric structure.

Assignees

• Micron Technology Inc

Inventors

• Meade Roy E

Classifications

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title

• H10W10/061

  using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10P90/1906 Primary

  Preparing SOI wafers · CPC title