Vertical p-type, n-type, p-type (PNP) junction integrated circuit (IC) structure

US10211324B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10211324-B2
Application numberUS-201715795884-A
CountryUS
Kind codeB2
Filing dateOct 27, 2017
Priority dateAug 12, 2014
Publication dateFeb 19, 2019
Grant dateFeb 19, 2019

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  1. Title

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  2. Abstract

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  5. First independent claim

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Abstract

Official abstract text for this publication.

Various particular embodiments include an integrated circuit (IC) structure having: a stack region; and a silicon substrate underlying and contacting the stack region, the silicon substrate including: a silicon region including a doped subcollector region; a set of isolation regions overlying the silicon region; a base region between the set of isolation regions and below the stack region, the base region including an intrinsic base contacting the stack region, an extrinsic base contacting the intrinsic base and the stack region, and an amorphized extrinsic base contact region contacting the extrinsic base; a collector region between the set of isolation regions; an undercut collector-base region between the set of isolation regions and below the base region; and a collector contact region contacting the collector region under the intrinsic base and the collector-base region via the doped subcollector region.

First claim

Opening claim text (preview).

We claim: 1. An integrated circuit (IC) structure comprising: a stack region; and a silicon substrate underlying and contacting the stack region, the silicon substrate including: a silicon region including a doped subcollector region; a set of isolation regions overlying the silicon region; a base region between the set of isolation regions and below the stack region, the base region including an intrinsic base contacting the stack region, an extrinsic base contacting the intrinsic base and the stack region, and an amorphized extrinsic base contact region contacting the extrinsic base; a collector region between the set of isolation regions; an undercut collector-base region between the set of isolation regions and below the base region; and a collector contact region contacting the collector region under the intrinsic base and the undercut collector-base region via the doped subcollector region, wherein the undercut collector-base region does not extend laterally beyond the amorphized extrinsic base contact region, and wherein the undercut collector-base region abuts one of the isolation regions in the set and the amorphized extrinsic base contact region. 2. An integrated circuit (IC) structure comprising: a stack region; and a silicon substrate underlying and contacting the stack region, the silicon substrate including: a silicon region including a doped subcollector region; a set of isolation regions overlying the silicon region; a base region between the set of isolation regions and below the stack region, the base region including an intrinsic base contacting the stack region, an extrinsic base contacting the intrinsic base and the stack region, and an amorphized extrinsic base contact region contacting the extrinsic base; a collector region between the set of isolation regions; an undercut collector-base region between the set of isolation regions and below the base region, wherein the undercut collector-base region does not extend laterally beyond the set of isolation regions; and a collector contact region contacting the collector region under the intrinsic base and the undercut collector-base region via the doped subcollector region, wherein the undercut collector-base region does not extend laterally beyond the amorphized extrinsic base contact region.

Assignees

Inventors

Classifications

  • by selectively depositing, e.g. by using selective CVD or plating · CPC title

  • of trenches having shapes other than rectangular or V-shape (H10W10/0143 takes precedence) · CPC title

  • formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

  • Electricity · mapped topic

  • Electricity · mapped topic

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What does patent US10211324B2 cover?
Various particular embodiments include an integrated circuit (IC) structure having: a stack region; and a silicon substrate underlying and contacting the stack region, the silicon substrate including: a silicon region including a doped subcollector region; a set of isolation regions overlying the silicon region; a base region between the set of isolation regions and below the stack region, the …
Who is the assignee on this patent?
IBM
What technology area does this patent fall under?
Primary CPC classification H01L29/732. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Feb 19 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).