Semiconductor device having a plurality of top surface connection terminals

Patent metadata

Field	Value
Publication number	US-10211144-B2
Application number	US-201615580457-A
Country	US
Kind code	B2
Filing date	Jul 4, 2016
Priority date	Jul 29, 2015
Publication date	Feb 19, 2019
Grant date	Feb 19, 2019

Abstract

This semiconductor device includes a semiconductor element mounted on a metal layer, first to third connection terminals that are provided on the semiconductor element, a first bus bar bonded to the first connection terminal, and a second bus bar bonded to the second connection terminal. The semiconductor element is bonded to the metal layer, and the first to third connection terminals are disposed on a top surface of the semiconductor element. One end of the first bus bar is bonded to the first connection terminal, another end of the first bus bar is an output unit, one end of the second bus bar is bonded to the second connection terminal, and another end of the second bus bar is bonded to the metal layer. A first surface of the semiconductor element and the second bus bar are at an identical potential.

First claim

The invention claimed is:

1. A semiconductor device comprising:
a metal layer which is a conductor;
a semiconductor element mounted on a first surface of the metal layer;
a first connection terminal provided on the semiconductor element;
a second connection terminal provided on the semiconductor element;
a third connection terminal provided on the semiconductor element;
a first bus bar bonded to the first connection terminal, the first bus bar formed as a single conductive member; and
a second bus bar bonded to the second connection terminal,
wherein a first surface of the semiconductor element is bonded to the first surface of the metal layer,
the first connection terminal, the second connection terminal, and the third connection terminal are disposed on a second surface of the semiconductor element,
one end of the first bus bar is bonded to the first connection terminal,
another end of the first bus bar is an output unit which is exposed to the outside of the semiconductor device,
one end of the second bus bar is bonded to the second connection terminal,
another end of the second bus bar is bonded to the metal layer, and
the first surface of the semiconductor element and the second bus bar are at an identical potential, and
a cross-sectional area of the second bus bar in a direction of electrical conduction is larger than a cross-sectional area of the first bus bar in a direction of electrical conduction.

2. The semiconductor device according to claim 1 , further comprising:
an insulating layer provided on a second surface of the metal layer; and
a heat dissipator provided to the insulating layer,
wherein a first surface of the insulating layer is in contact with the metal layer, and
a second surface of the insulating layer is in contact with the heat dissipator.

3. The semiconductor device according to claim 1 ,
wherein the semiconductor element is constituted by a gallium nitride-based transistor,
the first connection terminal is a drain terminal,
the second connection terminal is a source terminal, and
the third connection terminal is a gate terminal.

4. The semiconductor device according to claim 1 , wherein the metal layer is a lead frame in which a wiring pattern is formed.

5. The semiconductor device according to claim 1 , wherein
the second bus bar includes a plurality of linearly extending conductors and joint section,
a first conductor is one of the plurality of linearly extending conductors and extends horizontally with respect to the first surface of the semiconductor element,
a second conductor is another one of the plurality of linearly extending conductors and extends vertically with respect to the first surface of the semiconductor element, and
the first conductor and the second conductor are connected to each other by the joint section.

6. The semiconductor device according to claim 5 , wherein the first conductor is a rod shape or plate shape.

7. The semiconductor device according to claim 5 , wherein the second conductor is a rod shape or plate shape.

Assignees

• Panasonic Ip Man Co Ltd

Inventors

• Kohda Shinichi
• Kimura Junichi
• Usui Ryosuke
• Ogura Tomohide
• Watanabe Atsushi

Classifications

• H10W72/07636

  Soldering or alloying · CPC title

• H10W72/07336

  Soldering or alloying · CPC title

• H10W72/926

  Multiple bond pads having different sizes · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title

• H10W72/652

  comprising metals or metalloids, e.g. silver · CPC title