Semiconductor apparatus comprising a plurality of current sink units

Patent metadata

Field	Value
Publication number	US-10210927-B2
Application number	US-201715583476-A
Country	US
Kind code	B2
Filing date	May 1, 2017
Priority date	Aug 22, 2013
Publication date	Feb 19, 2019
Grant date	Feb 19, 2019

Abstract

A semiconductor memory apparatus includes a column address decoding unit configured to decode a column address and generate a column select signal; a row address decoding unit configured to decode a row address and generate a word line select signal; a driving driver unit configured to provide different voltages to a plurality of resistive memory elements in response to the column select signal; a sink current control unit configured to generate a plurality of sink voltages with different voltage levels in response to the word line select signal; and a plurality of current sink units configured to flow current from the plurality of respective resistive memory elements to a ground terminal in response to the plurality of sink voltages.

First claim

What is claimed is:

1. A processor, comprising:
a core unit configured to perform an operation corresponding to a command input from the outside using data according to the command;
a cache semiconductor device unit configured to store one or more among data to be operated, data corresponding to a result of the operation, and an address for the data to be operated; and
a bus interface configured to be connected between the core unit and the cache semiconductor device unit, and transmit data between the core unit and the cache semiconductor device unit,
wherein the cache semiconductor device unit includes a semiconductor memory apparatus comprising:
a driving driver unit configured to provide voltages with different voltage levels to a plurality of respective resistive memory elements, respectively, in response to a column select signal;
a plurality of current sink units configured to flow current from the plurality of respective resistive memory elements to a ground terminal in response to a plurality of sink voltages; and
a sink current control unit configured to generate the plurality of sink voltages with different voltage levels in response to a plurality of word line select signals.

2. The processor according to claim 1 ,
wherein the driving driver unit comprises:
a driving driver configured to provide a driving voltage in response to the column select signal, and
wherein the voltages with different voltage levels are provided to the plurality of respective resistive memory elements according to distances between the driving driver and the plurality of respective resistive memory elements.

3. The processor according to claim 2 , wherein the driving driver unit provides a voltage with a lower voltage level to a resistive memory element distant from the driving driver rather than to a resistive memory element close to the driving driver.

4. The processor according to claim 2 , wherein the plurality of current sink units are configured such that a current sink unit electrically coupled with a resistive memory element distant from the driving driver is applied with a sink voltage with a higher voltage level than a current sink unit electrically coupled with the resistive memory element close to the driving driver.

5. The processor according to claim 2 , wherein the sink current control unit outputs one of the plurality of sink voltages in response to a word line select signal which is enabled among the plurality of word line select signals.

6. The processor according to claim 5 , wherein the sink current control unit is configured to provide a sink voltage with a higher voltage level to a current sink unit electrically coupled with the resistive memory element distant from the driving driver than a current sink unit electrically coupled with the resistive memory element close to the driving driver.

7. The processor according to claim 6 , wherein the sink current control unit comprises:
a voltage supply signal generating section configured to generate a voltage supply signal when even one of the plurality of word line select signals is enabled;
a voltage dividing section configured to supply a first word line driving voltage and a second word line driving voltage to both ends, respectively, of a plurality of resistor elements electrically coupled in series, in response to the voltage supply signal, and generate the plurality of sink voltages; and
a plurality of switching sections configured to output one of the plurality of sink voltages in response to a word line select signal which is enabled among the plurality of word line select signals.

Assignees

• Sk Hynix Inc

Inventors

• Yoon Jung Hyuk
• Shin Yoon Jae

Classifications

• G11C11/16 Primary

  using elements in which the storage effect is based on magnetic spin effect · CPC title

• G11C11/1659

  Cell access · CPC title

• G11C13/0002

  using resistive RAM [RRAM] elements · CPC title

• G11C11/1653

  Address circuits or decoders · CPC title

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title