Display panel and driving method thereof and display apparatus

Patent metadata

Field	Value
Publication number	US-10210789-B2
Application number	US-201515129650-A
Country	US
Kind code	B2
Filing date	Dec 31, 2015
Priority date	Aug 6, 2015
Publication date	Feb 19, 2019
Grant date	Feb 19, 2019

Abstract

A display panel, driving method thereof and display apparatus are provided. The display panel comprises 4N gate lines, drive controlling circuit (1) connected to respective gate driving circuits and configured to output a group of timing control signals to respective gate driving circuits, and mode switching circuit (2) connected to drive controlling circuit (1), which can control drive controlling circuit (1) to drive all gate driving circuits to output scan signals sequentially to respective first gate line groups by taking two adjacent gate lines as first gate line group in scanning direction when receiving first mode control signal; and/or control drive controlling circuit (1) to drive all gate driving circuits to output scan signals sequentially to respective second gate line groups by taking four adjacent gate lines as second gate line group in scanning direction when receiving second mode control signal. Therefore, power consumption can be reduced, and standby-time can be prolonged.

First claim

What is claimed is:

1. A display panel, comprising 4N gate lines; a first gate driving circuit connected to a (4n+1)-th gate line and a third gate driving circuit connected to a (4n+3)-th gate line, which are located on one side of the display panel; a second gate driving circuit connected to a (4n+2)-th gate line and a fourth gate driving circuit connected to a (4n+4)-th gate line, which are located on another side of the display panel; and a drive controlling circuit connected to respective gate driving circuits and configured to at least output a group of timing control signals to the respective gate driving circuits, the group of timing control signals having one-to-one correspondence relationship with the respective gate driving circuits, where n is an integer greater than or equal to 0 and smaller than N, and further comprising: a mode switching circuit connected to the drive controlling circuit; wherein
the mode switching circuit is configured to control the drive controlling circuit to drive all the gate driving circuits to output scan signals sequentially to respective first gate line groups by taking two adjacent gate lines as the first gate line group in scanning direction when receiving a first mode control signal; and/or
the mode switching circuit is configured to control the drive controlling circuit to drive all the gate driving circuits to output scan signals sequentially to respective second gate line groups by taking adjacent four gate lines as the second gate line group in scanning direction when receiving a second mode control signal.

2. The display panel according to claim 1 , wherein respective groups of timing control signals comprise at least a trigger signal and a clock signal, and widths of trigger signals in the respective groups of timing control signals are the same, and the respective gate driving circuits are used to output scan signals to corresponding gate lines sequentially under the control of a received corresponding group of timing control signals.

3. The display panel according to claim 2 , wherein when receiving the first mode control signal, the mode switching circuit controls the drive controlling circuit to output a second group of timing control signals to the second gate driving circuit while outputting a first group of timing control signals to the first gate driving circuit, and to output a fourth group of timing control signals to the fourth gate driving circuit while outputting a third group of timing control signals to the third gate driving circuit; wherein
timings of respective signals in the first group of timing control signals are the same as timings of corresponding signals in the second group of timing control signals, timings of respective signals in the third group of timing control signal are the same as timings of corresponding signals in the fourth group of timing control signals, and timings of respective signals in the third group of timing control signals delay one trigger signal width compared with timings of corresponding signals in the first group of timing control signals.

4. The display panel according to claim 2 , wherein when receiving a second mode control signal, the mode switching circuit controls the drive controlling circuit to output the second group of timing control signals to the second gate driving circuit while outputting the first group of timing control signals to the first gate driving circuit, to output the third group of timing control signals to the third gate driving circuit, and to output the fourth group of timing control signals to the fourth gate driving circuit; wherein
timings of respective signals in the first group of timing control signals are the same as timings of corresponding signals in the second group of timing control signals, timings of corresponding signals in the third group of timing control signal, and timings of corresponding signal in the fourth group of timing control signals.

5. The display panel according to claim 2 , wherein the mode switching circuit is further configured to:
control the drive controlling circuit to drive all the gate driving circuits to output scan signals to the N gate lines sequentially in scanning direction when receiving the third mode control signal.

6. The display panel according to claim 5 , wherein when receiving the third mode control signal, the mode switching circuit controls the drive controlling circuit to output sequentially the first group of timing control signals to the first gate driving circuit, outputs the second group of timing control signals to the second gate driving circuit, outputs the third group of timing control signal to the third gate driving circuit, and output the fourth group of timing control signals to the fourth gate driving circuit sequentially; wherein
timings of respective signals in the second group of timing control signals delay one half trigger signal width compared with timings of corresponding signals in the first group of timing control signals; timings of respective signals in the third group of timing control signals delay one half trigger signal width compared with timings of corresponding signals in the second group of timing control signals; and timings of respective signals in the fourth group of timing control signals delay one half trigger signal width compared with timings of corresponding signals in the third timing control signal.

7. The display panel according to claim 1 , wherein the display panel is a liquid crystal display panel or an organic light-emitting display panel.

8. A driving method of the display panel according to claim 1 , comprising:
controlling the drive controlling circuit to drive all gate driving circuits to output scan signals sequentially to respective first gate line groups by taking two adjacent gate lines as the first gate line group in scanning direction when the mode switching circuit receives a first mode control signal;
controlling the drive controlling circuit to drive all the gate driving circuits to output scan signals sequentially to respective second gate line groups by taking adjacent four gate lines as the second gate line group in scanning direction when the mode switching circuit receives a second mode control signal; and
controlling the drive controlling circuit to drive all gate driving circuits to output scan signals sequentially to the N gate lines in scanning direction when the mode switching circuit receives a third mode control signal.

9. The driving method according to claim 8 , wherein
when the mode switching circuit receives a first mode control signal, the mode switching circuit controls the drive controlling circuit to output a second group of timing control signals to the second gate driving circuit while outputting a first group of timing control signals to the first gate driving circuit, and to output a fourth group of timing control signals to the fourth gate driving circuit while outputting a third group of timing control signals to the third gate driving circuit; wherein
timings of respective signals in the first group of timing control signals are the same as timings of corresponding signals in the second group of timing control signals, timings of respective signals in the third group of timing control signal are the same as timings of corresponding signals in the fourth group of timing control signals, and timings of respective signals in the third group of timing control signals delay one trigger signal width compared with the timings of corresponding signals in the first group of timing control signals.

10. The driving method according to claim 8 , wherein
when receiving a second mode control signal, the mode switching circuit controls the drive controlling circuit to o

Assignees

• Boe Technology Group Co Ltd
• Ordos Yuansheng Optoelectronics Co Ltd

Inventors

• Li Fuqiang
• Fan Jun
• Chen Xiaochuan
• Dong Xue

Classifications

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• G09G3/2092 Primary

  Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto (suitable for both CRT and flat panel G09G5/003; specific for a CRT G09G1/165) · CPC title

• G09G2310/0205

  Simultaneous scanning of several lines in flat panels · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G2310/0218

  with collection of electrodes in groups for n-dimensional addressing · CPC title