Semiconductor device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-10204979-B2
Application number	US-201715406552-A
Country	US
Kind code	B2
Filing date	Jan 13, 2017
Priority date	Dec 17, 2010
Publication date	Feb 12, 2019
Grant date	Feb 12, 2019

Abstract

A semiconductor device is disclosed. In a surface layer of a front surface of an n-type semiconductor substrate, an anode layer is provided in an element activation portion and an annular p-type guard ring and an n-type high-concentration surface region are provided in an annular termination breakdown voltage region which surrounds the outer circumference of the anode layer. The impurity concentration of the n-type high-concentration surface region is higher than that of the semiconductor substrate and is lower than that of the p-type guard ring. The depth of the n-type high-concentration surface region is less than that of the guard ring. The anode layer and the guard ring are formed while the oxygen concentration of the semiconductor substrate is set to be equal to or more than 1×10 16 /cm 3 and equal to or less than 1×10 18 /cm 3 .

First claim

The invention claimed is:

1. A semiconductor device comprising:
an n-type semiconductor substrate including an n-type drift layer;
an n-type high-concentration layer that is provided at a surface of one side of the substrate and adjacent to the drift layer, and includes vacancy-oxygen (VO) complex defects as donors, a concentration of the VO complex defects of the n-type high-concentration layer being higher than a concentration of VO complex defects of the substrate, the high-concentration layer having a doping concentration higher than a doping concentration of the n-type drift layer; and
a broad buffer (BB) layer provided within the n-type semiconductor substrate or adjacent to the n-type high-concentration layer toward another side of the substrate, and having impurities, a concentration of the impurities in a center portion of the BB layer in a thickness direction being higher than a concentration of the impurities in a portion of the BB layer distal to the center portion, a doping concentration of the BB layer being higher than the doping concentration of the n-type drift layer,
wherein the BB layer includes hydrogen atoms as donors.

2. The semiconductor device according to claim 1 , wherein the n-type high-concentration layer has an oxygen concentration in a range from 1×10 16 /cm 3 to 1×10 18 /cm 3 .

3. The semiconductor device according to claim 1 , further comprising a p-type guard ring that is formed at the one side of the substrate and contacts the n-type high-concentration layer.

4. The semiconductor device according to claim 3 , wherein a depth of the p-type guard ring is greater than that of the n-type high-concentration layer.

5. The semiconductor device according to claim 1 , wherein the n-type high-concentration layer is in direct contact with an uppermost surface of the substrate.

6. The semiconductor device according to claim 1 , wherein a maximum concentration of the impurities in the BB layer is in a range of 1×10 16 /cm 3 to 1×10 18 /cm 3 .

7. The semiconductor device according to claim 1 , wherein the BB layer includes a plurality of BB layers.

8. The semiconductor device according to claim 1 , wherein the center portion of the BB layer has a maximum concentration of the impurities.

Assignees

• Fuji Electric Co Ltd

Inventors

• Mizushima Tomonori

Classifications

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P32/171

  being group IV material · CPC title

• H10P32/18

  Diffusion lifetime killers · CPC title

• H10P30/208

  of electrically inactive species · CPC title

• H10P30/204

  into Group IV semiconductors · CPC title