Semiconductor device with dual work function gate stacks and method for fabricating the same

Patent metadata

Field	Value
Publication number	US-8962463-B2
Application number	US-201313845174-A
Country	US
Kind code	B2
Filing date	Mar 18, 2013
Priority date	Dec 27, 2012
Publication date	Feb 24, 2015
Grant date	Feb 24, 2015

Abstract

A method for fabricating a semiconductor device includes forming a gate dielectric layer over a substrate; forming a metal containing layer, containing an effective work function adjust species, over the gate dielectric layer; forming an anti-reaction layer over the metal containing layer; increasing an amount of the effective work function adjust species contained in the metal containing layer; and forming, on the substrate, a gate stack by etching the anti-reaction layer, the metal containing layer, and the gate dielectric layer.

First claim

What is claimed is:

1. A method for fabricating a semiconductor device, the method comprising:
forming a gate dielectric layer over a substrate;
forming a metal containing layer, containing an effective work function adjust species, over the gate dielectric layer;
forming an anti-reaction layer over the metal containing layer;
increasing an amount of the effective work function adjust species contained in the metal containing layer by annealing the metal containing layer in an atmosphere containing the effective work function adjust species; and
forming, on the substrate, a gate stack by etching the anti-reaction layer, the metal containing layer, and the gate dielectric layer after the annealing of the metal containing layer.

2. The method of claim 1 , wherein the effective work function adjust species comprises an effective work function increase species to increase an effective work function of the gate stack.

3. The method of any one of claim 1 , wherein the effective work function adjust species comprises nitrogen.

4. The method of claim 1 , wherein the metal containing layer comprises a nitrogen rich metal nitride, and the effective work function adjust species comprises nitrogen.

5. The method of claim 1 , wherein the metal containing layer comprises titanium nitride including nitrogen at a higher ratio than a chemical stoichiometric ratio of titanium to nitrogen.

6. The method of claim 1 , wherein the anti-reaction layer comprises polysilicon.

7. A method for fabricating a semiconductor device, the method comprising:
forming a gate dielectric layer on an entire surface of a substrate including a first region and a second region;
forming a nitrogen-rich first metal nitride layer over the gate dielectric layer;
forming an anti-reaction layer over the first metal nitride layer;
injecting an effective work function increase species into the nitrogen-rich first metal nitride layer;
removing the anti-reaction layer and the nitrogen-rich first metal nitride layer from the second region;
forming a metal-rich second metal nitride layer on an entire surface of a resultant structure, including the gate dielectric layer formed in the second region;
forming a first gate stack in the first region by etching the metal-rich second metal nitride layer, the anti-reaction layer, the nitrogen-rich first metal nitride layer, and the gate dielectric layer; and
forming a second gate stack in the second region by etching the metal-rich second metal nitride and the gate dielectric layer.

8. The method of claim 7 , wherein the nitrogen-rich first metal nitride comprises titanium nitride (TiN) containing nitrogen at a higher ratio than a chemical stoichiometric ratio of titanium to nitrogen.

9. The method of claim 7 , wherein the metal-rich second metal nitride comprises titanium nitride (TiN) containing titanium at a higher ratio than a chemical stoichiometric ratio of titanium to nitrogen.

10. The method of claim 7 , wherein the injecting an effective work function increase species comprises:
annealing the nitrogen-rich first metal nitride layer in a nitrogen containing atmosphere.

11. The method of claim 7 , wherein the anti-reaction layer comprises polysilicon.

12. A method for fabricating a semiconductor device, the method comprising:
forming a gate dielectric layer on an entire surface of a substrate comprising a first region and a second region;
forming a first metal containing layer containing a first effective work function adjust species
forming an anti-reaction layer over the gate dielectric layer;
increasing an amount of the first effective work function adjust species contained in the first metal containing layer;
removing the anti-reaction layer and the first metal containing layer from the second region;
forming a second metal containing layer, containing a second effective work function adjust species, on an entire surface of a resultant structure, including the gate dielectric layer formed in the second region;
forming a first gate stack in the first region by etching the second metal containing layer, the anti-reaction layer, the first metal containing layer, and the gate dielectric layer; and
forming a second gate stack in the second region by etching the second metal containing layer and the gate dielectric layer.

13. The method of claim 12 , wherein the increasing an amount of the first effective work function adjust species comprises:
annealing the first metal containing layer in an atmosphere containing the first effective work function adjust species.

14. The method of claim 12 , wherein the first effective work function adjust species comprises an effective work function increase species to increase an effective work function of the first gate stack.

15. The method of claim 12 , wherein the first effective work function adjust species comprises nitrogen.

16. The method of claim 12 , wherein the second effective work function adjust species comprises an effective work function decrease species to decrease an effective work function of the second gate stack.

17. The method of claim 12 , wherein the second effective work function adjust species comprises titanium.

18. The method of claim 12 , wherein the first metal containing layer comprises titanium nitride (TiN) including nitrogen at a higher ratio than a chemical stoichiometric ratio of titanium to nitrogen.

19. The method of claim 12 , wherein the second metal containing layer comprises titanium nitride (TiN) including titanium at a higher ratio than a chemical stoichiometric ratio of titanium to nitrogen.

20. The method of claim 12 , the anti-reaction layer comprises polysilicon.

21. The method of claim 12 , wherein the first gate stack comprises a gate stack of a P-channel transistor.

22. The method of claim 12 , wherein the second gate stack comprises a gate stack of an N-channel transistor.

Assignees

• Sk Hynix Inc

Inventors

• Ji Yun-Hyuck
• Jang Se-Aug
• Lee Seung-Mi
• Kim Hyung-Chul

Classifications

• H10D64/01318

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314) · CPC title

• H10D64/667

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671) · CPC title

• H10D84/0177

  the gate conductors having different materials or different implants · CPC title

• H10D64/01 Primary

  Manufacture or treatment · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title